Abstract: A pixel array substrate includes a first touch signal line having a first and second portion and a bridge portion, pixel structures including a first and second pixel structure, a first and second data line, a first and second connection pattern, and a touch electrode. The first pixel structure and the second pixel structure are respectively located on a first and second side of the first touch signal line. The first data line and the second data line are respectively located on the second and first sides of the first touch signal line. The first connection pattern is electrically connected to the first data line and the first pixel structure. The second connection pattern is electrically connected to the second data line and the second pixel structure. The bridge portion of the first touch signal line crosses over the first connection pattern and the second connection pattern.

Abstract: A pixel array substrate includes a first touch signal line having a first and second portion and a bridge portion, pixel structures including a first and second pixel structure, a first and second data line, a first and second connection pattern, and a touch electrode. The first pixel structure and the second pixel structure are respectively located on a first and second side of the first touch signal line. The first data line and the second data line are respectively located on the second and first sides of the first touch signal line. The first connection pattern is electrically connected to the first data line and the first pixel structure. The second connection pattern is electrically connected to the second data line and the second pixel structure. The bridge portion of the first touch signal line crosses over the first connection pattern and the second connection pattern.

Abstract: A data writing method for a solid state storage device includes following steps. A step (a) is performed to judge whether a shutdown command is issued from a host. In a step (b), if the solid state storage device confirms that the shutdown command is not issued from the host, plural program procedures are performed. Consequently, plural write data in a buffer are stored to a triple-level cell flash memory according to a program order. In a step (c), if the solid state storage device confirms that the shutdown command is issued from the host, plural redundant data are added to the plural write data, the write data are stored into the buffer, and the plural program procedures are performed. Consequently, the plural write data in the buffer are stored to the triple-level cell flash memory according to the program order.

Abstract: A data writing method for a solid state storage device includes following steps. A step (a) is performed to judge whether a shutdown command is issued from a host. In a step (b), if the solid state storage device confirms that the shutdown command is not issued from the host, plural program procedures are performed. Consequently, plural write data in a buffer are stored to a triple-level cell flash memory according to a program order. In a step (c), if the solid state storage device confirms that the shutdown command is issued from the host, plural redundant data are added to the plural write data, the write data are stored into the buffer, and the plural program procedures are performed. Consequently, the plural write data in the buffer are stored to the triple-level cell flash memory according to the program order.

Abstract: A dual-switch flyback power converter includes a control circuit to generate a switching signal. A high-side driving circuit includes a pulse generation circuit. The pulse generation circuit generates a pulse-on signal and a pulse-off signal to control two transistors in response to the switching signal. The two transistors further respectively provide a level-shift-on signal and a level-shift-off signal to a comparison circuit to enable/disable a high-side driving signal. Without using a charge pump circuit to power the high-side driving circuit, a floating winding of a transformer is utilized to provide a floating voltage to power the high-side driving circuit, which reduces the cost of the dual-switch flyback power converter and ensures a sufficient high-side driving capability of the high-side driving circuit.

Abstract: A parallel PFC converter comprises a first PFC circuit, a second PFC circuit, and a voltage divider. The second PFC circuit is connected in parallel with the first PFC circuit for generating an output voltage of the parallel PFC converter. The voltage divider is coupled to receive the output voltage for generating a first feedback signal and a second feedback signal. The first feedback signal is higher than the second feedback signal. The first PFC circuit and the second PFC circuit respectively comprises a first switching control circuit and a second switching control circuit for regulating the output voltage. It is an object of the present invention to reduce the power loss for improving the efficiency of the PFC converter.

Abstract: A dual-switch flyback power converter includes a control circuit to generate a switching signal. A high-side driving circuit includes a pulse generation circuit. The pulse generation circuit generates a pulse-on signal and a pulse-off signal to control two transistors in response to the switching signal. The two transistors further respectively provide a level-shift-on signal and a level-shift-off signal to a comparison circuit to enable/disable a high-side driving signal. Without using a charge pump circuit to power the high-side driving circuit, a floating winding of a transformer is utilized to provide a floating voltage to power the high-side driving circuit, which reduces the cost of the dual-switch flyback power converter and ensures a sufficient high-side driving capability of the high-side driving circuit.