Abstract: The invention discloses a reticle pod including a base and a lid mounted to the base. The base has a bottom surface having at least one first mark and at least one second mark. The first mark has a first reflectivity relative to a light source, and the second mark has a second reflectivity relative to the light source. The first reflectivity is different from the second reflectivity, and both are also different from that of the rest area of the bottom surface.

Abstract: A storage device for generating an identity code and an identity code generating method are disclosed. The storage device includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores a plurality of first data and the first data have a plurality of bits. The second storage circuit stores a plurality of second data and the second data have a plurality of bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, selects a first portion of the first data according to the first sequence, reads the first portion of the first data from the first storage circuit to form a target sequence and outputs the target sequence to serve as an identity code.

Abstract: An apparatus includes a six-axis correction stage, an auto-collimation measurement device, a light splitter, a telecentric image measurement device, and a controller. The six-axis correction stage carries a device under test; the auto-collimation measurement device is arranged above the six-axis correction stage along a measurement optical axis; the light splitter is arranged on the measurement optical axis and is interposed between the six-axis correction stage and the auto-collimation measurement device. A method controls the six-axis correction stage to correct rotation errors in at least two degrees of freedom of the device under test according to a measurement result of the auto-collimation measurement device, and controls the six-axis correction stage to correct translation and yaw errors in at least three degrees of freedom of the device under test according to a measurement result of the telecentric image measurement device by means of the controller.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

Abstract: An automatic heating vending machine including a storage space, a storage mechanism, a fetching mechanism, a gripping arm mechanism, a rotating disc mechanism and a heating mechanism are disclosed. The storage mechanism is installed in the storage space to store food. The fetching mechanism is installed in the storage space and disposed under the storage mechanism to catch the food. The gripping arm mechanism grips the food on the fetching mechanism. The rotating disc mechanism is disposed on one side of the gripping arm mechanism. The gripping arm mechanism grips the food and then places the food on the rotating disc mechanism. The heating mechanism is disposed above the rotating disc mechanism. After the food has been placed on the rotating disc mechanism, the rotating disc mechanism undergoes horizontal movement and vertical movement, allowing the food to be admitted to the heating mechanism and heated.

Abstract: A pixel array substrate includes a first touch signal line having a first and second portion and a bridge portion, pixel structures including a first and second pixel structure, a first and second data line, a first and second connection pattern, and a touch electrode. The first pixel structure and the second pixel structure are respectively located on a first and second side of the first touch signal line. The first data line and the second data line are respectively located on the second and first sides of the first touch signal line. The first connection pattern is electrically connected to the first data line and the first pixel structure. The second connection pattern is electrically connected to the second data line and the second pixel structure. The bridge portion of the first touch signal line crosses over the first connection pattern and the second connection pattern.

Abstract: A pixel array substrate includes a first touch signal line having a first and second portion and a bridge portion, pixel structures including a first and second pixel structure, a first and second data line, a first and second connection pattern, and a touch electrode. The first pixel structure and the second pixel structure are respectively located on a first and second side of the first touch signal line. The first data line and the second data line are respectively located on the second and first sides of the first touch signal line. The first connection pattern is electrically connected to the first data line and the first pixel structure. The second connection pattern is electrically connected to the second data line and the second pixel structure. The bridge portion of the first touch signal line crosses over the first connection pattern and the second connection pattern.

Abstract: A data writing method for a solid state storage device includes following steps. A step (a) is performed to judge whether a shutdown command is issued from a host. In a step (b), if the solid state storage device confirms that the shutdown command is not issued from the host, plural program procedures are performed. Consequently, plural write data in a buffer are stored to a triple-level cell flash memory according to a program order. In a step (c), if the solid state storage device confirms that the shutdown command is issued from the host, plural redundant data are added to the plural write data, the write data are stored into the buffer, and the plural program procedures are performed. Consequently, the plural write data in the buffer are stored to the triple-level cell flash memory according to the program order.

Abstract: A data writing method for a solid state storage device includes following steps. A step (a) is performed to judge whether a shutdown command is issued from a host. In a step (b), if the solid state storage device confirms that the shutdown command is not issued from the host, plural program procedures are performed. Consequently, plural write data in a buffer are stored to a triple-level cell flash memory according to a program order. In a step (c), if the solid state storage device confirms that the shutdown command is issued from the host, plural redundant data are added to the plural write data, the write data are stored into the buffer, and the plural program procedures are performed. Consequently, the plural write data in the buffer are stored to the triple-level cell flash memory according to the program order.

Abstract: A dual-switch flyback power converter includes a control circuit to generate a switching signal. A high-side driving circuit includes a pulse generation circuit. The pulse generation circuit generates a pulse-on signal and a pulse-off signal to control two transistors in response to the switching signal. The two transistors further respectively provide a level-shift-on signal and a level-shift-off signal to a comparison circuit to enable/disable a high-side driving signal. Without using a charge pump circuit to power the high-side driving circuit, a floating winding of a transformer is utilized to provide a floating voltage to power the high-side driving circuit, which reduces the cost of the dual-switch flyback power converter and ensures a sufficient high-side driving capability of the high-side driving circuit.

Abstract: A parallel PFC converter comprises a first PFC circuit, a second PFC circuit, and a voltage divider. The second PFC circuit is connected in parallel with the first PFC circuit for generating an output voltage of the parallel PFC converter. The voltage divider is coupled to receive the output voltage for generating a first feedback signal and a second feedback signal. The first feedback signal is higher than the second feedback signal. The first PFC circuit and the second PFC circuit respectively comprises a first switching control circuit and a second switching control circuit for regulating the output voltage. It is an object of the present invention to reduce the power loss for improving the efficiency of the PFC converter.

Abstract: A dual-switch flyback power converter includes a control circuit to generate a switching signal. A high-side driving circuit includes a pulse generation circuit. The pulse generation circuit generates a pulse-on signal and a pulse-off signal to control two transistors in response to the switching signal. The two transistors further respectively provide a level-shift-on signal and a level-shift-off signal to a comparison circuit to enable/disable a high-side driving signal. Without using a charge pump circuit to power the high-side driving circuit, a floating winding of a transformer is utilized to provide a floating voltage to power the high-side driving circuit, which reduces the cost of the dual-switch flyback power converter and ensures a sufficient high-side driving capability of the high-side driving circuit.