Abstract: In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.

Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.

Abstract: Impurities in a liquefied solid fuel utilized in a droplet generator of an extreme ultraviolet photolithography system are removed from vessels containing the liquefied solid fuel. Removal of the impurities increases the stability and predictability of droplet formation which positively impacts wafer yield and droplet generator lifetime.

Abstract: A method of fabricating a semiconductor device is provided. Recesses are formed in a substrate. A first gate dielectric material is formed on the substrate and filled in the recesses. The first gate dielectric material on the substrate between the recesses is at least partially removed to form a trench. A second gate dielectric material is formed in the trench. A gate conductive layer is formed on the second gate dielectric material. Spacers are formed on sidewalls of the gate conductive layer. A portion of the first gate dielectric material is removed. The remaining first gate dielectric material and the second gate dielectric layer form a gate dielectric layer. The gate dielectric layer includes a body part and a first hump part at a first edge of the body part. The first hump part is thicker than the body part. Doped regions are formed in the substrate beside the spacers.

Abstract: An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably couple with an MDI circuit to conduct data communication with a respondent-side circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation according to the instruction of the processing circuit to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit.

Abstract: An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably conduct data communication with a respondent-side circuit through an MDI circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit, and arranged to operably generate an echo cancellation signal.

Abstract: The present disclosure discloses a media communication apparatus having built-in signal synchronization mechanism. A local clock generation circuit generates a reference clock signal and a media clock signal. A time calibration circuit performs time calibration process with an external apparatus to generate time calibration information to further calibrate the reference clock signal and the media clock signal accordingly to generate a calibrated reference clock signal and a calibrated media clock signal on a standard time domain. A media clock processing circuit generates a sampling signal according to the calibrated media clock signal. A signal processing circuit generates time related information according to the calibrated reference clock signal to process an input media signal according to the time related information and the sampling signal and generate an output media signal.

Abstract: A power supplying method for a computer system is proposed. The computer system includes a first computer node, a first power supply unit corresponding to the first computer node, a second computer node, a second power supply unit corresponding to the second computer node, and a connection module electrically connected to the computer nodes and the power supply units. The power supplying method includes: detecting, by the first computer node, whether the second power supply unit operates abnormally; and upon detecting at least that the second power supply unit operates abnormally, controlling, by the first computer node, the first power supply unit to provide electric power to the second computer node through the connection module.

Abstract: A power supplying method for a computer system is proposed. The computer system includes a first computer node, a first power supply unit corresponding to the first computer node, a second computer node, a second power supply unit corresponding to the second computer node, and a connection module electrically connected to the computer nodes and the power supply units. The power supplying method includes: detecting, by the first computer node, whether the second power supply unit operates abnormally; and upon detecting at least that the second power supply unit operates abnormally, controlling, by the first computer node, the first power supply unit to provide electric power to the second computer node through the connection module.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.