Patents by Inventor Ming-Hsuan Tsai

Ming-Hsuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240195449
    Abstract: An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably conduct data communication with a respondent-side circuit through an MDI circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit, and arranged to operably generate an echo cancellation signal.
    Type: Application
    Filed: December 4, 2023
    Publication date: June 13, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yuan-Jih CHU, Yao-Chun CHUANG, Ching-Yen LEE, Ming Hsuan TSAI
  • Publication number: 20240195450
    Abstract: An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably couple with an MDI circuit to conduct data communication with a respondent-side circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation according to the instruction of the processing circuit to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit.
    Type: Application
    Filed: December 4, 2023
    Publication date: June 13, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yuan-Jih CHU, Yao-Chun CHUANG, Ching-Yen LEE, Ming Hsuan TSAI
  • Publication number: 20240178847
    Abstract: The present disclosure discloses a media communication apparatus having built-in signal synchronization mechanism. A local clock generation circuit generates a reference clock signal and a media clock signal. A time calibration circuit performs time calibration process with an external apparatus to generate time calibration information to further calibrate the reference clock signal and the media clock signal accordingly to generate a calibrated reference clock signal and a calibrated media clock signal on a standard time domain. A media clock processing circuit generates a sampling signal according to the calibrated media clock signal. A signal processing circuit generates time related information according to the calibrated reference clock signal to process an input media signal according to the time related information and the sampling signal and generate an output media signal.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 30, 2024
    Inventors: MING-JHE DU, Ming-Hsuan Tsai, Chun-I Yeh, Yu-Chong Yen
  • Patent number: 10942555
    Abstract: A power supplying method for a computer system is proposed. The computer system includes a first computer node, a first power supply unit corresponding to the first computer node, a second computer node, a second power supply unit corresponding to the second computer node, and a connection module electrically connected to the computer nodes and the power supply units. The power supplying method includes: detecting, by the first computer node, whether the second power supply unit operates abnormally; and upon detecting at least that the second power supply unit operates abnormally, controlling, by the first computer node, the first power supply unit to provide electric power to the second computer node through the connection module.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 9, 2021
    Assignee: Mitac Computing Technology Corporation
    Inventors: Ming-Li Tsai, Jyun-Jie Wang, Cheng-Tung Wang, Chia-Ming Liu, Ming-Hsuan Tsai
  • Publication number: 20190121413
    Abstract: A power supplying method for a computer system is proposed. The computer system includes a first computer node, a first power supply unit corresponding to the first computer node, a second computer node, a second power supply unit corresponding to the second computer node, and a connection module electrically connected to the computer nodes and the power supply units. The power supplying method includes: detecting, by the first computer node, whether the second power supply unit operates abnormally; and upon detecting at least that the second power supply unit operates abnormally, controlling, by the first computer node, the first power supply unit to provide electric power to the second computer node through the connection module.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 25, 2019
    Inventors: Ming-Li TSAI, Jyun-Jie WANG, Cheng-Tung WANG, Chia-Ming LIU, Ming-Hsuan TSAI
  • Publication number: 20120083088
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
    Type: Application
    Filed: September 22, 2011
    Publication date: April 5, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hsuan Tsai, Chun-Fai Cheng, Hui Ouyang, Yuan-Hung Chiu, Yen-Ming Chen