Patents by Inventor Ming-Hsun Lee
Ming-Hsun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133745Abstract: A temperature sensing device includes a substrate, a first reflective module, a first window cover, and a dual thermopile sensor. The first reflective module is disposed on the substrate, including a first mirror chamber with a narrow field of view (FOV), and the first reflective module focuses a thermal radiation from measured object to a first image plane in the first mirror chamber. The first window cover is disposed on the first reflective module, and the first window cover allows a selected band of the thermal radiation to pass through. The dual thermopile sensor is disposed on the substrate and located in the first mirror chamber, and the dual thermopile sensor senses a temperature data from the first image plane. Additional second reflective module, LED source plus pin hole with same FOV of dual thermopile sensor can illuminate the measured object for ease of placement of object to be heated.Type: ApplicationFiled: October 19, 2022Publication date: April 25, 2024Inventors: Chein-Hsun WANG, Ming LE, Tung-Yang LEE, Yu-Chih LIANG, Wen-Chie HUANG, Chen-Tang HUANG, Jenping KU
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Patent number: 11961770Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: GrantFiled: November 4, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
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Publication number: 20240107666Abstract: A circuit board includes a first electronic component and a circuit substrate. The first electrode component includes two electrodes. The circuit substrate includes an inner substrate and an outer substrate formed on the inner substrate. The inner substrate defines a receiving cavity, and the first electronic component received in the receiving cavity. Each electrode faces an inner sidewall of the receiving cavity. The inner substrate includes a first insulating layer and a blocking layer embedded in the first insulating layer, an end of the blocking layer exposed from the inner sidewall. The outer substrate defines two through holes. Each through hole passes through a portion of the first insulating layer connected to the inner sidewall and exposes the blocking layer. A top end of each of the two electrodes facing the outer substrate is partially received in one through hole.Type: ApplicationFiled: November 28, 2022Publication date: March 28, 2024Inventors: MING-HSUN LEE, CHEN-EN LIN
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Patent number: 11929767Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.Type: GrantFiled: August 16, 2022Date of Patent: March 12, 2024Assignee: MEDIATEK INC.Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
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Patent number: 11852944Abstract: An electrochromic module includes two opposite positioned first substrates and at least one electrochromic unit disposed between the first substrates. Each of the electrochromic unit includes a first conductive layer, a filter layer, and a second conductive layer stacked in turn. One end of the first conductive layer protrudes from an edge of the filter layer to form a first electrode area. One end of the second conductive layer protrudes from another edge of the filter layer to form a second electrode area. Vertical projections of the first electrode area and the second electrode area on the first substrates are spaced apart from each other. Each of the first electrode area and the second electrode area is configured to connect to a power supply. The electrochromic module can make it easy to connect the electrochromic unit to the power supply.Type: GrantFiled: July 14, 2021Date of Patent: December 26, 2023Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN) CO.LTD.Inventors: Ming-Hsun Lee, Yen-Lin Peng
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Patent number: 11736785Abstract: A camera module includes a circuit board, a bracket arranged on the circuit board, and at least one electronic component embedded in the bracket and/or arranged on an inner side wall of the bracket. The electronic component is electrically coupled to the circuit board.Type: GrantFiled: March 26, 2021Date of Patent: August 22, 2023Assignee: TRIPLE WIN TECHNOLOGY (SHENZHEN) CO. LTD.Inventor: Ming-Hsun Lee
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Publication number: 20230074175Abstract: A method for controlling a concentration of donors in an Al-alloyed gallium oxide crystal structure includes implanting a Group IV element as a donor impurity into the crystal structure with an ion implantation process and annealing the implanted crystal structure to activate the Group IV element to form an electrically conductive region. The method may further include depositing one or more electrically conductive materials on at least a portion of the implanted crystal structure to form an ohmic contact. Examples of semiconductor devices are also disclosed and include a layer of an Al-alloyed gallium oxide crystal structure, at least one region including the crystal structure implanted with a Group IV element as a donor impurity with an ion implantation process and annealed to activate the Group IV element, an ohmic contact including one or more electrically conductive materials deposited on the at least one region.Type: ApplicationFiled: September 8, 2022Publication date: March 9, 2023Inventors: Rebecca L. PETERSON, Ming-Hsun LEE, Alan G. JACOBS, Marko J. TADJER
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Patent number: 11573784Abstract: An electronic device for updating on-board data of power off status is provided, which combines a rewritable memory, an embedded controller, and a second network socket onto a motherboard. The rewritable memory includes a target storage area. The embedded controller includes a second network interface electrically connected to the second network socket, for receiving a writing command and a binary file. After receiving power of a standby mode, the embedded controller executes a data writing program to receive the writing command and the binary file via the second network socket and the second network interface, and writes the binary data file into the target storage area of the rewritable memory by using the data writing program.Type: GrantFiled: December 9, 2019Date of Patent: February 7, 2023Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.Inventors: Chih-Jen Hou, Hsin-Teng Fu, Ming-Hsun Lee, Shang-Wen Wu, Dee-Lun Tsai
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Publication number: 20220232147Abstract: A camera module includes a circuit board, a bracket arranged on the circuit board, and at least one electronic component embedded in the bracket and/or arranged on an inner side wall of the bracket. The electronic component is electrically coupled to the circuit board.Type: ApplicationFiled: March 26, 2021Publication date: July 21, 2022Inventor: MING-HSUN LEE
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Publication number: 20220019116Abstract: An electrochromic module includes two opposite positioned first substrates and at least one electrochromic unit disposed between the first substrates. Each of the electrochromic unit includes a first conductive layer, a filter layer, and a second conductive layer stacked in turn. One end of the first conductive layer protrudes from an edge of the filter layer to form a first electrode area. One end of the second conductive layer protrudes from another edge of the filter layer to form a second electrode area. Vertical projections of the first electrode area and the second electrode area on the first substrates are spaced apart from each other. Each of the first electrode area and the second electrode area is configured to connect to a power supply. The electrochromic module can make it easy to connect the electrochromic unit to the power supply.Type: ApplicationFiled: July 14, 2021Publication date: January 20, 2022Inventors: MING-HSUN LEE, YEN-LIN PENG
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Publication number: 20200344368Abstract: An image processing device able to receive image and other data wirelessly for more reliable communication includes at least one a camera module and at least one a processing module. The camera module includes a lens, an image sensor configured for converting the captured light into electrical signals and a first integrated unit. The at least one processing module includes a processor configured for generating signals of an image according to the electrical signals, and a second integrated unit. The first integrated unit and the second integrated unit establish a non-contact wireless communication connection therebetween, thereby realizing communicating between the camera module and the processing module.Type: ApplicationFiled: July 9, 2019Publication date: October 29, 2020Inventors: YING-LIN CHEN, MING-HSUN LEE
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Publication number: 20200201623Abstract: An electronic device for updating on-board data of power off status is provided, which combines a rewritable memory, an embedded controller, and a second network socket onto a motherboard. The rewritable memory includes a target storage area. The embedded controller includes a second network interface electrically connected to the second network socket, for receiving a writing command and a binary file. After receiving power of a standby mode, the embedded controller executes a data writing program to receive the writing command and the binary file via the second network socket and the second network interface, and writes the binary data file into the target storage area of the rewritable memory by using the data writing program.Type: ApplicationFiled: December 9, 2019Publication date: June 25, 2020Inventors: Chih-Jen Hou, Hsin-Teng Fu, Ming-Hsun Lee, Shang-Wen Wu, Dee-Lun Tsai
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Patent number: 10623646Abstract: A camera system includes a lens unit, an image sensor, a sensing unit, an adjustment unit, a memory, and a controller. The lens unit focuses reflected light to form an image. The image sensor converts the image formed by the lens unit into a digital image. The sensing unit senses an internal temperature of the camera system and an external temperature outside the camera system. The adjustment unit adjusts the lens unit. The memory stores preset adjustment amounts for adjusting the lens unit according to different internal temperatures of the camera system operating at different external temperatures. The controller receives the internal temperature and the external temperature sensed by the sensing unit, retrieves the corresponding preset adjustment amount from the memory according to the sensed temperatures, and controls the adjustment unit to adjust the lens unit according to the preset adjustment amount.Type: GrantFiled: May 14, 2019Date of Patent: April 14, 2020Assignee: TRIPLE WIN TECHNOLOGY (SHENZHEN) CO. LTD.Inventors: Ming-Hsun Lee, Yen-Lin Peng
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Patent number: 9909305Abstract: A composite wall assembly has an auxiliary wall and an inner wall. The auxiliary wall has a hollow space and a first supporting pillar having multiple first through holes. The inner wall is attached to the auxiliary wall and forms a depositing space. The inner wall has a first wall member, a second wall member, and a second supporting pillar having multiple second through holes. The depositing space is formed between the first wall member and the second wall member. The auxiliary wall provides a cushion effect and is not damaged easily in the earthquake for protecting the pipelines in the hollow space. The interior ambient temperature of the building is lowered by the hollow space of the auxiliary wall.Type: GrantFiled: June 13, 2017Date of Patent: March 6, 2018Inventor: Ming-Hsun Lee
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Publication number: 20170362823Abstract: A composite wall assembly has an auxiliary wall and an inner wall. The auxiliary wall has a hollow space and a first supporting pillar having multiple first through holes. The inner wall is attached to the auxiliary wall and forms a depositing space. The inner wall has a first wall member, a second wall member, and a second supporting pillar having multiple second through holes. The depositing space is formed between the first wall member and the second wall member. The auxiliary wall provides a cushion effect and is not damaged easily in the earthquake for protecting the pipelines in the hollow space. The interior ambient temperature of the building is lowered by the hollow space of the auxiliary wall.Type: ApplicationFiled: June 13, 2017Publication date: December 21, 2017Inventor: Ming-Hsun Lee
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Patent number: 8575739Abstract: A semiconductor package is disclosed including a leadframe, memory die and controller die, one or more of which are customized to facilitate electrical connection of the memory and controller die bond pads to the contact pads of the host device via the leadframe. By customizing one or more of the leadframe, memory die and controller die, an interposer layer normally required to connect the die in the semiconductor package with a host device may be omitted.Type: GrantFiled: May 6, 2011Date of Patent: November 5, 2013Assignee: SanDisk Technologies Inc.Inventors: Suresh Upadhyayula, Ming Hsun Lee, Hem Takiar
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Publication number: 20120280378Abstract: A semiconductor package is disclosed including a leadframe, memory die and controller die, one or more of which are customized to facilitate electrical connection of the memory and controller die bond pads to the contact pads of the host device via the leadframe. By customizing one or more of the leadframe, memory die and controller die, an interposer layer normally required to connect the die in the semiconductor package with a host device may be omitted.Type: ApplicationFiled: May 6, 2011Publication date: November 8, 2012Inventors: Suresh Upadhyayula, Ming Hsun Lee, Hem Takiar
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Patent number: 8097495Abstract: A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.Type: GrantFiled: April 1, 2008Date of Patent: January 17, 2012Assignee: SanDisk Technologies Inc.Inventors: Ming Hsun Lee, Chih-Chin Liao, Cheemen Yu, Hem Takiar
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Patent number: 7728411Abstract: A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include one or more semiconductor die having die attach pads along a single side. The leadframe may include a plurality of elongated electrical leads, extending from a first side of the leadframe, beneath the die, and terminating at a second side of the leadframe adjacent to the bond pads along the single edge of the die. The leadframe may further include a dielectric spacer layer on the elongated leads. Spacing the semiconductor die from the elongated leads using the spacer layer reduces the parasitic capacitance and/or inductance of the semiconductor package formed thereby.Type: GrantFiled: February 15, 2006Date of Patent: June 1, 2010Assignee: SanDisk CorporationInventors: Ming Hsun Lee, Cheemen Yu, Hem Takiar
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Publication number: 20090166820Abstract: A method of fabricating a semiconductor leadframe package from a strip including multiply encapsulated leadframe packages, and a leadframe package formed thereby are disclosed. An entire row or column of leadframes gets encapsulated together. Encapsulating an entire row or column reduces the keep-out area between adjacent leadframe packages, which allows the internal leads of each leadframe and the semiconductor die coupled thereto to be lengthened.Type: ApplicationFiled: December 27, 2007Publication date: July 2, 2009Inventors: Hem Takiar, Shrikar Bhagath, Ming Hsun Lee, Bonnie Ming-Yan Chan