Patents by Inventor Ming-Hua Wang
Ming-Hua Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240387405Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure having a dielectric structure and multiple wiring layers in or over the dielectric structure and a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure also includes a first chip structure bonded to the redistribution structure and electrically insulated from the shield bump structure, and the first chip structure has a first sidewall. The chip package structure further includes a second chip structure bonded to the redistribution structure and electrically insulated from the shield bump structure. The first chip structure and the second chip structure are spaced apart from each other by a gap, and the shield bump structure extends across the gap. The first sidewall faces away from the second chip structure, and the shield bump structure extends across the first sidewall.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Inventors: Po-Chen LAI, Chin-Hua WANG, Ming-Chih YEW, Chia-Kuei HSU, Li-Ling LIAO, Po-Yao LIN, Shin-Puu JENG
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Publication number: 20240379496Abstract: A package assembly includes an interposer module on a package substrate, a liquid alloy thermal interface material (TIM) on the interposer module, a seal ring surrounding the liquid alloy TIM, and a package lid on the liquid alloy TIM and seal ring, wherein the seal ring, interposer module and package lid seal the liquid alloy TIM.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Chin-Hua WANG, Yu-Sheng LIN, Po-Yao LIN, Ming-Chih YEW, Shin-Puu JENG
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Publication number: 20240381605Abstract: A fan-out package includes a redistribution structure having redistribution-side bonding structures, a plurality of semiconductor dies including a respective set of die-side bonding structures that is attached to a respective subset of the redistribution-side bonding structures through a respective set of solder material portions, and an underfill material portion laterally surrounding the redistribution-side bonding structures and the die-side bonding structures of the plurality of semiconductor dies. A subset of the redistribution-side bonding structures is not bonded to any of the die-side bonding structures of the plurality of semiconductor dies and is laterally surrounded by the underfill material portion, and is used to provide uniform distribution of the underfill material during formation of the underfill material portion.Type: ApplicationFiled: July 21, 2024Publication date: November 14, 2024Inventors: Ming-Chih YEW, Shu-Shen YEH, Chin-Hua WANG, Po-Yao LIN, Shin-Puu JENG
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Publication number: 20240379820Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
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Publication number: 20240369421Abstract: The present disclosure provides embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a dielectric layer and a fin-shaped structure disposed over the dielectric layer. The fin-shaped structure includes a first p-type doped region, a second p-type doped region, and a third p-type doped region, and a first n-type doped region, a second n-type doped region, and a third n-type doped region interleaving the first p-type doped region, the second p-type doped region, and the third p-type doped region. The first p-type doped region, the third p-type doped region and the third n-type doped region are electrically coupled to a first potential. The second p-type doped region, the first n-type doped region and the second n-type doped region are electrically coupled to a second potential different from the first potential.Type: ApplicationFiled: July 12, 2024Publication date: November 7, 2024Inventors: Zi-Ang Su, Ming-Shuan Li, Shu-Hua Wu, Chih Chieh Yeh, Chih-Hung Wang, Wen-Hsing Hsieh
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Publication number: 20240347407Abstract: Structures and formation methods of a chip package structure are provided. The method includes mounting semiconductor dies over die regions of an interposer substrate. The adjacent die regions are separated from one another by a gap region of the interposer substrate. The method also includes forming first underfill material layers and a second gap-filling layer over the interposer substrate corresponding to the gap region. The method further includes forming an encapsulating layer over the interposer substrate to surround the semiconductor dies, the first underfill material layers, and the second underfill material layer. The gap region has ends and the first underfill material layers is formed adjacent to the ends of the gap region. The Young's modulus of the second underfill material layer is less than that of the first underfill material layers.Type: ApplicationFiled: June 25, 2024Publication date: October 17, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Chen LAI, Ming-Chih YEW, Po-Yao LIN, Chin-Hua WANG, Shin-Puu JENG
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Patent number: 12113033Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The chip package structure includes a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure includes a first chip structure bonded to the redistribution structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure partially overlaps the shield bump structure. The chip package structure includes a second chip structure bonded to the redistribution structure.Type: GrantFiled: June 29, 2023Date of Patent: October 8, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Chen Lai, Chin-Hua Wang, Ming-Chih Yew, Chia-Kuei Hsu, Li-Ling Liao, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 12107149Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.Type: GrantFiled: April 18, 2023Date of Patent: October 1, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
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Publication number: 20240297089Abstract: A package structure is provided. The package structure includes a package component over a redistribution structure, a substrate under the redistribution structure, and an underfill material over the redistribution structure and including a first extending portion in the structure. The package component has a first sidewall and a second sidewall connected to the first sidewall at a first corner. In a plan view, the first extending portion has a first sidewall passing through the first sidewall of the package component and a second sidewall opposite to the first sidewall of the first extending portion and passing through the second sidewall of the package component.Type: ApplicationFiled: May 13, 2024Publication date: September 5, 2024Inventors: Po-Chen LAI, Ming-Chih YEW, Li-Ling LIAO, Chin-Hua WANG, Po-Yao LIN, Shin-Puu JENG
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Patent number: 12078551Abstract: The present disclosure provides embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a dielectric layer and a fin-shaped structure disposed over the dielectric layer. The fin-shaped structure includes a first p-type doped region, a second p-type doped region, and a third p-type doped region, and a first n-type doped region, a second n-type doped region, and a third n-type doped region interleaving the first p-type doped region, the second p-type doped region, and the third p-type doped region. The first p-type doped region, the third p-type doped region and the third n-type doped region are electrically coupled to a first potential. The second p-type doped region, the first n-type doped region and the second n-type doped region are electrically coupled to a second potential different from the first potential.Type: GrantFiled: October 13, 2020Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zi-Ang Su, Ming-Shuan Li, Shu-Hua Wu, Chih Chieh Yeh, Chih-Hung Wang, Wen-Hsing Hsieh
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Publication number: 20240290869Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.Type: ApplicationFiled: April 23, 2024Publication date: August 29, 2024Inventors: Chen-Huang Huang, Ming-Jhe Sie, Cheng-Chung Chang, Shao-Hua Hsu, Shu-Uei Jang, An Chyi Wei, Shiang-Bau Wang, Ryan Chia-Jen Chen
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Patent number: 12057363Abstract: Structures and formation methods of a chip package structure are provided. The chip package structure includes an interposer substrate including first and second die regions that are separated by a gap region. The chip package structure also includes first and second semiconductor dies respectively arranged over the first and second die regions. In addition, the chip package structure includes first and second gap-filling layers formed over the gap region and separated from one another, and a third gap-filling layer over the gap region and between the first and second gap-filling layers. The Young's modulus of the third gap-filling layer is less than the Young's modulus of the first gap-filling layer and the Young's modulus of the second gap-filling layer.Type: GrantFiled: August 31, 2021Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Chen Lai, Ming-Chih Yew, Po-Yao Lin, Chin-Hua Wang, Shin-Puu Jeng
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Publication number: 20240258193Abstract: A method of forming a semiconductor package structure is provided. The method includes disposing a first semiconductor device on an interposer substrate, disposing the interposer substrate on a carrier substrate, applying a thermal interface material on the first semiconductor device, and attaching a lid on the carrier substrate to cover the first semiconductor device. The interposer substrate is disposed between the carrier substrate and the first semiconductor device. The lid includes a lower surface having a first recess facing the first semiconductor device, and a portion of the thermal interface material is accommodated in the first recess.Type: ApplicationFiled: April 10, 2024Publication date: August 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chen LAI, Ming-Chih YEW, Po-Yao LIN, Chin-Hua WANG, Shin-Puu JENG
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Publication number: 20240249983Abstract: A light-emitting device includes a substrate, a light-emitting diode, a first layer, a color filter layer, and a second layer. The light-emitting diode is disposed on the substrate. The first layer is disposed on the substrate and has an opening. At least a portion of the light-emitting diode is disposed in the opening of the first layer. The color filter layer is disposed on the light-emitting diode. The second layer is disposed on the first layer and has an opening overlapped with the opening of the first layer. The second layer is configured to shield light emitted from the light-emitting diode. In the cross-sectional view of the light-emitting device, the minimum width of the opening of the first layer is less than the minimum width of the opening of the second layer.Type: ApplicationFiled: April 2, 2024Publication date: July 25, 2024Inventors: Tung-Kai LIU, Tsau-Hua HSIEH, Wei-Cheng CHU, Chun-Hsien LIN, Chandra LIUS, Ting-Kai HUNG, Kuan-Feng LEE, Ming-Chang LIN, Tzu-Min YAN, Hui-Chieh WANG
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Patent number: 11198702Abstract: A method for separating hydrolysis product of biomass is provided. The method includes providing a mixture solution containing a hydrolysis product of biomass and a divalent metal salt, adjusting the pH value of the mixture solution to between 1-4.6, and performing a filtering procedure on the mixture solution using a nanofiltration membrane to obtain a concentrated solution and a filtrate, wherein the concentrated solution mainly includes the hydrolysis product of biomass and the filtrate mainly includes the divalent metal salt.Type: GrantFiled: February 3, 2017Date of Patent: December 14, 2021Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yen-Ting Kuo, Hou-Peng Wan, Tzu-Yueh Yang, Chien-Yuan Su, Ming-Hua Wang
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Publication number: 20170226144Abstract: A method for separating hydrolysis product of biomass is provided. The method includes providing a mixture solution containing a hydrolysis product of biomass and a divalent metal salt, adjusting the pH value of the mixture solution to between 1-4.6, and performing a filtering procedure on the mixture solution using a nanofiltration membrane to obtain a concentrated solution and a filtrate, wherein the concentrated solution mainly includes the hydrolysis product of biomass and the filtrate mainly includes the divalent metal salt.Type: ApplicationFiled: February 3, 2017Publication date: August 10, 2017Applicant: Industrial Technology Research InstituteInventors: Yen-Ting KUO, Hou-Peng WAN, Tzu-Yueh YANG, Chien-Yuan SU, Ming-Hua WANG
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Publication number: 20110037731Abstract: An electronic device and an operating method thereof are provided. The method firstly establishes a database recording at least one predefined operating gesture, a predefined function corresponding to the predefined operating gesture, and a specific color. An image captured by an image capturing unit of the electronic device is then obtained. When the specific color is found in the image, a position of the specific color is obtained and a gesture trajectory is displayed on a screen of the electronic device according to the position. The method repeats the steps of obtaining the image and displaying the gesture trajectory till it is unable to find the specific color in the currently obtained image. By referring to the database, the predefined function is then executed according to the predefined operating gesture which is determined by connecting the positions of the specific color in the obtained images.Type: ApplicationFiled: July 22, 2010Publication date: February 17, 2011Applicant: Inventec Appliances Corp.Inventors: MING-HUA WANG, Li Yu, Tony Tsai
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Patent number: 7364560Abstract: An ambulatory hip fixation-traction splint frame includes a supporting frame having an upper end arranged for positioning below an armpit of a treated patient and a lower end arranged for positioning below a hip portion of the treated patient, and a side splint assembly for supporting a side body of the treated patient. The side splint assembly includes a flexible guiding frame having first and second ends, and a curved guiding surface, having a predetermined curvature, defining between the first and second ends for biasing against the side body of the treated patient, and two coupling joints adjustably mounted on the supporting frame to connect with the first and second ends of the guiding frame respectively so as to retain the curvature of the guiding surface of the guiding frame for fitting on the side body of the treated patient.Type: GrantFiled: February 23, 2004Date of Patent: April 29, 2008Inventor: Ming-Hua Wang
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Patent number: 7087030Abstract: An ambulatory hip fixation-traction splint set includes a supporting frame having an upper end arranged for positioning below an armpit of a treated patient and a lower end extending to position below a hip portion of the treated patient, and a side splint assembly including a flexible guiding frame having first and second end portions mounted to the supporting frame wherein the guiding frame has a curved guiding surface adapted for fixing on a side body of the treated patient to retain the side body thereof at a fixation position. Therefore, the ambulatory hip fixation-traction splint set not only keeps the fracture area of the patient in fixation position but also assists the patient to have a suitable movement so as to enhance the recovery of the fracture area.Type: GrantFiled: February 7, 2003Date of Patent: August 8, 2006Inventor: Ming-Hua Wang
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Publication number: 20060046641Abstract: A screen protection apparatus equipped with character information transmission and calendar memo function is located in a mobile communication device. It includes a condition setting module, a display module, an information storing module, an information access module, a timer and a switch module. The condition setting module aims to set the mobile communication device in a screen protection state. The display module aims to display a protection picture on the display screen of the mobile communication device. The information storing module stores a plurality of information. The information access module accesses information in the information storing module when the mobile communication device is in the screen protection state, and display the protection picture on the display screen. The timer measures a switch time according to a preset time interval.Type: ApplicationFiled: September 1, 2004Publication date: March 2, 2006Inventors: David Ho, Tony Tsai, Ming-Hua Wang