Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, where the metal gate structure is surrounded by an interlayer dielectric (ILD) layer, where gate spacers extend along opposing sidewalls of the metal gate structure; recessing the metal gate structure and the gate spacers below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first material over the metal gate structure and over the gate spacers; forming a second material over the first material, where an upper surface of the second material is level with the upper surface of the ILD layer; and removing a first portion of the ILD layer adjacent to the metal gate structure to form an opening that exposes a source/drain region at a first side of the metal gate structure.

Abstract: A semiconductor device includes: a semiconductor fin extending along a first lateral direction; a gate structure extending along a second lateral direction perpendicular to the first lateral direction and straddling the semiconductor fin; an epitaxial structure disposed in the semiconductor fin and next to the gate structure; a first interconnect structure extending along the second lateral direction and disposed above the epitaxial structure; and a dielectric layer including a first portion and a second portion that form a stair.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, where the metal gate structure is surrounded by an interlayer dielectric (ILD) layer, where gate spacers extend along opposing sidewalls of the metal gate structure; recessing the metal gate structure and the gate spacers below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first material over the metal gate structure and over the gate spacers; forming a second material over the first material, where an upper surface of the second material is level with the upper surface of the ILD layer; and removing a first portion of the ILD layer adjacent to the metal gate structure to form an opening that exposes a source/drain region at a first side of the metal gate structure.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

Abstract: A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.

Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

Abstract: A method includes forming a first fin and a second fin protruding from a substrate; forming an isolation layer surrounding the first fin and the second fin; epitaxially growing a first epitaxial region on the first fin and a second epitaxial region on the second fin, wherein the first epitaxial region and the second epitaxial region are merged together; performing an etching process on the first epitaxial region and the second epitaxial region, wherein the etching process separates the first epitaxial region from the second epitaxial region; depositing a dielectric material between the first epitaxial region and the second epitaxial region; and forming a first gate stack extending over the first fin.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

Abstract: A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, where the metal gate structure is surrounded by an interlayer dielectric (ILD) layer, where gate spacers extend along opposing sidewalls of the metal gate structure; recessing the metal gate structure and the gate spacers below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first material over the metal gate structure and over the gate spacers; forming a second material over the first material, where an upper surface of the second material is level with the upper surface of the ILD layer; and removing a first portion of the ILD layer adjacent to the metal gate structure to form an opening that exposes a source/drain region at a first side of the metal gate structure.

Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

Abstract: A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.

Abstract: A method of forming a semiconductor device is provided. The method includes forming a recess in a substrate and forming a first dielectric layer in the recess. A portion of the first dielectric layer is removed. A second dielectric layer is formed over the first dielectric layer. A gate structure is formed over the second dielectric layer.

Abstract: A FinFET and methods for forming a FinFET are disclosed. A method includes forming trenches in a semiconductor substrate to form a fin, depositing an insulating material within the trenches, and removing a portion of the insulating material to expose sidewalls of the fin. The method also includes recessing a portion of the exposed sidewalls of the fin to form multiple recessed surfaces on the exposed sidewalls of the fin, wherein adjacent recessed surfaces of the multiple recessed surfaces are separated by a lattice shift. The method also includes depositing a gate dielectric on the recessed portion of the sidewalls of the fin and depositing a gate electrode on the gate dielectric.

Abstract: An embodiment fin field effect transistor (finFET) includes a fin extending upwards from a semiconductor substrate and a gate stack. The fin includes a channel region. The gate stack is disposed over and covers sidewalls of the channel region. The channel region includes at least two different semiconductor materials.