Abstract: A method of patterning a gate electrode layer having an underlying high-k dielectric layer comprising the following sequential steps. A substrate is provided. A high-k dielectric layer is formed over the substrate. A gate electrode layer is formed over the high-k dielectric layer. The gate electrode layer is patterned to form a patterned gate electrode layer, the patterned gate electrode layer having exposed side walls and a top. Sidewall spacers are formed over the exposed side walls of the patterned gate electrode layer, the sidewall spacers having tops. The patterned gate electrode layer is etched to pull the top of the patterned gate electrode layer down from the tops of the sidewall spacers. The exposed portions of the high-k dielectric layer not under the sidewall spacers and the pulled-down patterned gate electrode layer are removed.