Abstract: A power saving clock buffer comprises a first control stage installed between a clock output and a first switch stage for controlling the state of the first switch stage. A second switch stage installed between the clock output and a second switch stage for controlling the state of the second switch stage. A clock input stage is formed by connecting an PMOS with a NMOSs, and is installed between a clock input and the first and second switch stages and is connected to the clock output through a phase inverting logic circuit. By the aforementioned circuit structure, the clock circuit will stop working as the related circuit does not work and, therefore, the power is saved and a high reliability is attained.