Patents by Inventor Ming-Huei Shen
Ming-Huei Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10204822Abstract: In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed. The trench is partially filled with a flowable oxide to a level below the top surface of the semiconductor substrate, and the flowable oxide in the trench is cured. The negatively-charged liner above the cured flowable oxide is optionally removed. A silicon oxide is deposited in the remaining portion of the trench, and a planarization process is performed to remove excess portions of the silicon oxide over the top surface of the semiconductor substrate.Type: GrantFiled: January 30, 2018Date of Patent: February 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hsien Chou, Hung-Ling Shih, Tsun-Kai Tsao, Ming-Huei Shen, Kuo-Hwa Tzeng, Yeur-Luen Tu
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Publication number: 20180174888Abstract: In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed. The trench is partially filled with a flowable oxide to a level below the top surface of the semiconductor substrate, and the flowable oxide in the trench is cured. The negatively-charged liner above the cured flowable oxide is optionally removed. A silicon oxide is deposited in the remaining portion of the trench, and a planarization process is performed to remove excess portions of the silicon oxide over the top surface of the semiconductor substrate.Type: ApplicationFiled: January 30, 2018Publication date: June 21, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hsien CHOU, Hung-Ling SHIH, Tsun-Kai TSAO, Ming-Huei SHEN, Kuo-Hwa TZENG, Yeur-Luen TU
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Patent number: 9917003Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.Type: GrantFiled: June 28, 2013Date of Patent: March 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hsien Chou, Hung-Ling Shih, Tsun-Kai Tsao, Ming-Huei Shen, Kuo-Hwa Tzeng, Yeur-Luen Tu
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Patent number: 9525130Abstract: A phase change memory (“PCM”) cell is provided in accordance with some embodiments. The PCM includes a spacer defining a reaction area; a phase change material layer disposed within the reaction area; a protection layer disposed over the phase change material layer and within the reaction area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.Type: GrantFiled: January 6, 2015Date of Patent: December 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsun-Kai Tsao, Ming-Huei Shen, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
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Patent number: 9159735Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.Type: GrantFiled: July 18, 2013Date of Patent: October 13, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yong-Shiuan Tsair, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Tsun-Kai Tsao, Ming-Huei Shen
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Publication number: 20150115215Abstract: A phase change memory (“PCM”) cell is provided in accordance with some embodiments. The PCM includes a spacer defining a reaction area; a phase change material layer disposed within the reaction area; a protection layer disposed over the phase change material layer and within the reaction area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.Type: ApplicationFiled: January 6, 2015Publication date: April 30, 2015Inventors: Tsun-Kai Tsao, Ming-Huei Shen, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
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Publication number: 20150021679Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.Type: ApplicationFiled: July 18, 2013Publication date: January 22, 2015Inventors: Yong-Shiuan Tsair, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Tsun-Kai Tsao, Ming-Huei Shen
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Patent number: 8932900Abstract: A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.Type: GrantFiled: August 24, 2011Date of Patent: January 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsun-Kai Tsao, Ming-Huei Shen, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
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Patent number: 8932897Abstract: A phase change memory cell includes a first contact, a phase change region above and in contact with the first contact, an electrode region, and a second contact above and in contact with the electrode region. The phase change region surrounds the electrode region. The electrode region has a first surface in contact with the phase change region and a second surface in contact with the second contact, and the second surface is wider than the first surface.Type: GrantFiled: February 20, 2014Date of Patent: January 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huei Shen, Tsun Kai Tsao, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20150001669Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Cheng-Hsien Chou, Hung-Ling Shih, Tsun-Kai Tsao, Ming-Huei Shen, Kuo-Hwa Tzeng, Yeur-Luen Tu
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Publication number: 20140166970Abstract: A phase change memory cell includes a first contact, a phase change region above and in contact with the first contact, an electrode region, and a second contact above and in contact with the electrode region. The phase change region surrounds the electrode region. The electrode region has a first surface in contact with the phase change region and a second surface in contact with the second contact, and the second surface is wider than the first surface.Type: ApplicationFiled: February 20, 2014Publication date: June 19, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Huei SHEN, Tsun Kai TSAO, Shih-Chang LIU, Chia-Shiung TSAI
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Patent number: 8685783Abstract: On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer.Type: GrantFiled: October 27, 2010Date of Patent: April 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huei Shen, Tsun Kai Tsao, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20130048936Abstract: A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsun-Kai Tsao, Ming-Huei Shen, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
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Patent number: 8288750Abstract: A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided.Type: GrantFiled: April 29, 2010Date of Patent: October 16, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huei Shen, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 8273625Abstract: A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.Type: GrantFiled: April 9, 2010Date of Patent: September 25, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huei Shen, Tsun-Kai Tsao, Shih-Chang Liu, Chi-Hsin Lo, Chia-Shiung Tsai
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Publication number: 20120104339Abstract: On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer.Type: ApplicationFiled: October 27, 2010Publication date: May 3, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Huei SHEN, Tsun Kai TSAO, Shih-Chang LIU, Chia-Shiung TSAI
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Publication number: 20110266511Abstract: A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided.Type: ApplicationFiled: April 29, 2010Publication date: November 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Huei Shen, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20110248328Abstract: A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.Type: ApplicationFiled: April 9, 2010Publication date: October 13, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Huei Shen, Tsun Kai Tsao, Shih-Chang Liu, Chi-Hsin Lo, Chia-Shiung Tsai