Abstract: A method for growing a transition metal dichalcogenide layer involves arranging a substrate having a first transition metal contained pad is arranged in a chemical vapor deposition chamber. A chalcogen contained precursor is arranged upstream of the substrate in the chemical vapor deposition chamber. The chemical vapor deposition chamber is heated for a period of time during which a transition metal dichalcogenides layer, containing transition metal from the first transition metal contained pad and chalcogen from the chalcogen contained precursor, is formed in an area adjacent to the first transition metal contained pad.

Abstract: A method for growing a transition metal dichalcogenide layer involves arranging a substrate having a first transition metal contained pad is arranged in a chemical vapor deposition chamber. A chalcogen contained precursor is arranged upstream of the substrate in the chemical vapor deposition chamber. The chemical vapor deposition chamber is heated for a period of time during which a transition metal dichalcogenides layer, containing transition metal from the first transition metal contained pad and chalcogen from the chalcogen contained precursor, is formed in an area adjacent to the first transition metal contained pad.

Abstract: A device comprising: at least one first layer, such as a graphene layer, at least one second layer of transition metal dichalcogenide, wherein the at least one first layer and the at least one second layer of transition metal dichalcogenide form at least one heterojunction. The first and second layers are laterally displaced but may overlap over a length of 0 nm to 500 nm. A low-resistance contact is formed. The device can be a transistor including a field effect transistor. The layers can be formed by chemical vapor deposition. The graphene can be heavily p-doped. Transistor performance data are described.

Abstract: A device comprising: at least one first layer, such as a graphene layer, at least one second layer of transition metal dichalcogenide, wherein the at least one first layer and the at least one second layer of transition metal dichalcogenide form at least one heterojunction. The first and second layers are laterally displaced but may overlap over a length of 0 nm to 500 nm. A low-resistance contact is formed. The device can be a transistor including a field effect transistor. The layers can be formed by chemical vapor deposition. The graphene can be heavily p-doped. Transistor performance data are described.

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system is a redundancy array of independent disk 0 (RAID 0) system. The disk array system includes a plurality of disks. The data processing method includes: receiving a reading command; determining whether to divide the reading command to a plurality of reading command segments according to the reading command; and assigning the reading command to a corresponding disk of the disks to read data stored in the corresponding disk accordingly when it is determined that the reading command is not divided.

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system includes a first disk and a second disk. The data processing method includes: receiving a reading command, wherein the reading, command includes a data starting address; determining to assign the reading command to the first disk or the second disk according to the data starting address of the reading command and a stripe size; and reading corresponding data according to the reading command from the first disk or the second disk which receives the reading command.

Abstract: An anti-timeout method applied to a data processing system is provided. The data processing system includes a disk module. The anti-timeout method includes following steps: setting a total volume of the disk module into a plurality of virtual disk volumes, wherein each of the virtual disk volumes includes an instruction temporary storing queue for temporarily storing operating instructions corresponding to each virtual disk volume; selecting one of the instruction temporary storing queues and processing the operating instructions stored in the selected instruction temporary storing queue; calculating a continuous operating value of continuous processing of the selected instruction temporary storing queue; and selecting another one of the instruction temporary storing queues if the continuous operating value exceeds a predetermined threshold value.

Abstract: An anti-timeout method applied to a data processing system is provided. The data processing system includes a disk module. The anti-timeout method includes following steps: setting a total volume of the disk module into a plurality of virtual disk volumes, wherein each of the virtual disk volumes includes an instruction temporary storing queue for temporarily storing operating instructions corresponding to each virtual disk volume; selecting one of the instruction temporary storing queues and processing the operating instructions stored in the selected instruction temporary storing queue; calculating a continuous operating, value of continuous processing of the selected instruction temporary storing queue; and selecting another one of the instruction temporary storing queues if the continuous operating value exceeds a predetermined threshold value.

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system is a redundancy array of independent disk 0 (RAID 0) system The disk array system includes a plurality of disks. The data processing method includes: receiving a reading command; determining whether to divide the reading command to a plurality of reading command segments according to the reading command; and assigning the reading command to a corresponding disk of the disks to read data stored in the corresponding disk accordingly when it is determined that the reading command is not divided.

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system includes a first disk and a second disk The data processing method includes: receiving a reading command, wherein the reading, command includes a data starting address; determining to assign the reading command to the first disk or the second disk according to the data starting address of the reading command. and a stripe size; and reading corresponding data according to the reading command from the first disk or the second disk which receives the reading command.

Abstract: A data transmission device and a command merging method for data transmission are provided. The data transmission device includes a command register and a command merging unit. The command register receives and temporary storages a plurality of original commands, wherein the original commands include a plurality of memory blocks. When the command merging unit judges these memory blocks of the original commands to be a continuous memory block, the command merging unit merges the original commands into a merging command, and transmits the merging command to a peripheral device. Thus, the multiple commands send by the host can be analyzed and merged by the data transmission device to decrease a number of the commands to be proceed by the peripheral device, so as to speed up a command processing time of the peripheral device efficiently.

Abstract: A solar cell includes a substrate. The substrate has a light-receiving surface and a back surface opposite to the light-receiving surface. The substrate includes plural trenches formed on the back surface. The solar cell includes plural n-type diffusion areas and plural p-type diffusion areas alternately disposed on the back surface and the surface of the trenches. The possibility of recombination of the electron-hole pair while moving can be reduced because of the trenches, which are formed in the substrate.

Abstract: A data transmission device and a command merging method for data transmission are provided. The data transmission device includes a command register and a command merging unit. The command register receives and temporary storages a plurality of original commands, wherein the original commands include a plurality of memory blocks. When the command merging unit judges these memory blocks of the original commands to be a continuous memory block, the command merging unit merges the original commands into a merging command, and transmits the merging command to a peripheral device. Thus, the multiple commands send by the host can be analyzed and merged by the data transmission device to decrease a number of the commands to be proceed by the peripheral device, so as to speed up a command processing time of the peripheral device efficiently.

Abstract: A method of fabricating a solar cell is provided. A first type substrate having a first surface and a second surface is provided. A first doping process is performed on the first surface of the first type substrate by using a first dopant, so as to form a first type lightly doped layer. A second doping process is performed on a portion of the first type lightly doped layer by using a second dopant, so as to form a second type heavily doped region. A molecular weight of the second dopant is larger than a molecular weight of the first dopant, and a temperature of the first doping process is higher than a temperature of the second doping process. A first electrode is formed on the second type heavily doped region. A second electrode is formed on the second surface of the first type substrate.

Abstract: The disclosure is related to a method for transforming voltage identification codes of a microprocessor. The method comprises the steps of: receiving a first voltage identification code of a first voltage regulation standard, wherein the first voltage identification code is in correspondence with a first voltage; and transforming the first voltage identification code into a second voltage identification code of a second voltage regulation standard, wherein the second voltage identification code is in correspondence with a second voltage, and the second voltage is the same as the first voltage.

Abstract: The invention relates to a method for converting a voltage identification code includes the steps as follows. A special binary code range is obtained, and N special voltage identification codes corresponding to a special command are converted to N special binary codes under a converting relation, and the N special binary codes are used as the special binary code range. A first voltage identification code is converted to a corresponding first binary code under the converting relation. In addition, the first binary code and a first preset value are used to compute to obtain a second binary code, and the second binary code is not in the special binary code range.

Abstract: The invention relates to a method for converting a voltage identification code includes the steps as follows. A special binary code range is obtained, and N special voltage identification codes corresponding to a special command are converted to N special binary codes under a converting relation, and the N special binary codes are used as the special binary code range. A first voltage identification code is converted to a corresponding first binary code under the converting relation. In addition, the first binary code and a first preset value are used to compute to obtain a second binary code, and the second binary code is not in the special binary code range.

Abstract: The disclosure is related to a method for transforming voltage identification codes of a microprocessor. The method comprises the steps of: receiving a first voltage identification code of a first voltage regulation standard, wherein the first voltage identification code is in correspondence with a first voltage; and transforming the first voltage identification code into a second voltage identification code of a second voltage regulation standard, wherein the second voltage identification code is in correspondence with a second voltage, and the second voltage is the same as the first voltage.

Abstract: A VID processor includes a plurality of buffers, comparators, multiplexers and a core processing unit. The buffer may store a plurality of parameter values and a plurality of offset values. The buffers storing the parameter values may be coupled to the corresponding comparators, and other buffers may be coupled to the corresponding multiplexers. The comparator may compare the VID with the parameter values in the coupled buffer and output a selecting signal to the corresponding multiplexer according to the comparison outcome. Thus, the multiplexer may select and output one of the offset values to the core processing unit from the coupled buffer to allow the core processing unit to adjust the VID according to the output of the multiplexer.

Abstract: A case for accommodating a camera includes a wrist cuff, a connector secured to the wrist cuff, and a strap having opposite ends coupled to the connector. The wrist cuff includes two elastic members, and a through hole with two openings at opposite ends of the through hole. The elastic members are arranged at opposite end portions of the wrist cuff for closing the openings when the elastic members are in normal state, and the elastic members are deformable so as to open the openings.