Patents by Inventor Ming-Hui Shen
Ming-Hui Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9257568Abstract: A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.Type: GrantFiled: April 1, 2013Date of Patent: February 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hui Shen, Shih-Chang Liu, Chi-Hsin Lo, Chia-Shiung Tsai, Tsun Kai Tsao
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Patent number: 8445953Abstract: A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.Type: GrantFiled: April 22, 2010Date of Patent: May 21, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hui Shen, Shih-Chang Liu, Chi-Hsin Lo, Chia-Shiung Tsai, Tsun Kai Tsao
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Patent number: 8334560Abstract: Circuits and methods for providing a floating gate structure comprising floating gate cells having improved reverse tunnel disturb immunity. A floating gate structure is formed over a semiconductor substrate comprising a floating gate, a charge trapping dielectric layer is formed, and a control gate is formed. The floating gate structure has vertical sidewalls, one side adjacent a source region and one side adjacent a drain region. A symmetric sidewall dielectric is formed over the floating gate structure on both the source side and drain side regions. An asymmetric dielectric layer is formed over the drain side sidewall only. The use of the asymmetric sidewall on the drain side sidewall provides improved RTD immunity. Methods for forming the structure are disclosed.Type: GrantFiled: July 1, 2010Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Yu Pan, Chung-Jen Hwang, Ming-Hui Shen
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Patent number: 8227850Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.Type: GrantFiled: March 12, 2010Date of Patent: July 24, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chang Liu, Ming-Hui Shen, Chi-Hsin Lo, Chia-Shiung Tsai, Yi-Shin Chu
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Publication number: 20110049603Abstract: Circuits and methods for providing a floating gate structure comprising floating gate cells having improved reverse tunnel disturb immunity. A floating gate structure is formed over a semiconductor substrate comprising a floating gate, a charge trapping dielectric layer is formed, and a control gate is formed. The floating gate structure has vertical sidewalls, one side adjacent a source region and one side adjacent a drain region. A symmetric sidewall dielectric is formed over the floating gate structure on both the source side and drain side regions. An asymmetric dielectric layer is formed over the drain side sidewall only. The use of the asymmetric sidewall on the drain side sidewall provides improved RTD immunity. Methods for forming the structure are disclosed.Type: ApplicationFiled: July 1, 2010Publication date: March 3, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Yu Pan, Chung-Jen Hwang, Ming-Hui Shen
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Publication number: 20110006355Abstract: A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.Type: ApplicationFiled: April 22, 2010Publication date: January 13, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hui Shen, Shih-Chang Liu, Chi-Hsin Lo, Chia-Shiung Tsai, Tsun Kai Tsao
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Publication number: 20100171167Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.Type: ApplicationFiled: March 12, 2010Publication date: July 8, 2010Inventors: Shih-Chang Liu, Ming-Hui Shen, Chi-Hsin Lo, Chia-Shiung Tsai, Yi-Shin Chu
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Patent number: 7700473Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.Type: GrantFiled: April 9, 2007Date of Patent: April 20, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chang Liu, Ming-Hui Shen, Chi-Hsin Lo, Chia-Shiung Tsai, Yi-Shin Chu
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Publication number: 20080248620Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.Type: ApplicationFiled: April 9, 2007Publication date: October 9, 2008Inventors: Shih-Chang Liu, Ming-Hui Shen, Chi-Hsin Lo, Chia-Shiung Tsai, Yi-Shin Chu