Abstract: A semiconductor substrate including a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor is provided. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor.

Abstract: A touch display apparatus including a touch display panel and a control circuit is provided. The touch display panel includes a touch display array, a gate driver, and a sleep driving circuit. The gate driver is coupled to the touch display array to sequentially provide a plurality of gate driving signals. The sleep driving circuit is coupled to the touch display array. The control circuit is coupled to the gate driver and the sleep driving circuit. When the touch display apparatus enters a sleep state, the sleep driving circuit is turned on. The control circuit cuts off the gate driver during a display period and transmits a driving pulse to the touch display array through the sleep driving circuit during a touch sensing period.

Abstract: A shift register includes a first switch and a second switch coupled to a first node, a pull-down circuit selectively connecting the first node to a voltage end according to a potential of a second node, a control circuit, and an input stage circuit which may receive a previous-stage shift register output signal, a next-stage shift register output signal, and at least one scanning order logic signal. The first switch receives clock signals. A first output end of the input stage circuit outputs the previous-stage shift register output signal or the next-stage shift register output signal to a control end of the second switch based on the scanning order logic signal. The previous-stage shift register output signal or the next-stage shift register output signal triggers a second output end of the input stage circuit to output the scanning order logic signal to an input end of the control circuit.

Abstract: A pixel structure includes a scan line, a data line, a switching element, a planarization layer, a first common electrode, a common line, a first insulating layer, a pixel electrode, a second insulating layer, and a second common electrode. The switching element includes a source and a drain. The common line is located on the planarization layer and directly connected with the first common electrode. The planarization layer is located on the scan line, the data line, and the switching element. The pixel electrode is electrically connected with the drain through a first contact hole, wherein the first contact hole penetrates through the planarization layer and the first insulating layer. The second common electrode is electrically connected with the first common electrode through a second contact hole, wherein the second contact hole penetrates through the first insulating layer and the second insulating layer. A touch panel is also provided.

Abstract: A pixel structure disposed on a substrate having a pixel sensor region and a pixel display region disposed beside the pixel sensor region is provided. The pixel structure includes a pixel defining layer, a light-emitting diode, a pixel driving circuit and a sensor device. The pixel defining layer is disposed on the substrate and has a device accommodation portion located in the pixel display region. The light-emitting diode is disposed on the device accommodation portion. The area of the light-emitting diode is smaller than that of the device accommodation portion. The pixel driving circuit is disposed on the substrate, is electrically connected to the light-emitting diode, and includes a pixel electrode by which the device accommodation portion is covered. The light-emitting diode is bonded onto the pixel electrode. The sensor device is disposed between the pixel defining layer and the substrate and located in the pixel sensor region.

Abstract: A touch display panel having a display region, a peripheral region surrounding the display region, and a sensing region located between the display region and the peripheral region is provided. The touch display panel includes a pixel array, a touch electrode, an active device, at least one first sensor, at least one second sensor, and a light-shielding layer. The pixel array is located in the display region. The touch electrode located in the sensing region and the pixel array are separated from each other. The active device coupled to the touch electrode is located in the sensing region. The at least one first sensor and the at least one second sensor are located in the sensing region and separated from each other. The light-shielding layer covers the at least one first sensor.

Abstract: A display panel includes a substrate, an opening, a first gate driving circuit, a second gate driving circuit, a plurality of first gate lines, a plurality of second gate lines, and a plurality of third gate lines. The substrate has a display area, a first peripheral region, and a second peripheral region. The opening is located in the display area. The first gate driving circuit is located in the first peripheral region. The second gate driving circuit is located in the second peripheral region. The first gate lines are located between the opening and the first gate driving circuit. The second gate lines are located between the opening and the second gate driving circuit. The third gate lines are located between the first gate driving circuit and the second gate driving circuit.

Abstract: A shift register includes a first switch and a second switch coupled to a first node, a pull-down circuit selectively connecting the first node to a voltage end according to a potential of a second node, a control circuit, and an input stage circuit which may receive a previous-stage shift register output signal, a next-stage shift register output signal, and at least one scanning order logic signal. The first switch receives clock signals. A first output end of the input stage circuit outputs the previous-stage shift register output signal or the next-stage shift register output signal to a control end of the second switch based on the scanning order logic signal. The previous-stage shift register output signal or the next-stage shift register output signal triggers a second output end of the input stage circuit to output the scanning order logic signal to an input end of the control circuit.

Abstract: A display panel and a pixel circuit thereof are provided. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixel circuits. Each of the pixel circuits is coupled to corresponding gate line and data line. Each of the pixel circuits includes a first gate line and a pull-low switch. The first gate line is coupled to a control terminal of a driving transistor, and provides a first gate signal to drive the driving transistor during a driving time period. The pull-low switch pulls low the first gate signal to a reference low voltage according to a second gate signal on a second gate line when the driving time period finishes.

Abstract: A touch display apparatus including a touch display panel and a control circuit is provided. The touch display panel includes a touch display array, a gate driver, and a sleep driving circuit. The gate driver is coupled to the touch display array to sequentially provide a plurality of gate driving signals. The sleep driving circuit is coupled to the touch display array. The control circuit is coupled to the gate driver and the sleep driving circuit. When the touch display apparatus enters a sleep state, the sleep driving circuit is turned on. The control circuit cuts off the gate driver during a display period and transmits a driving pulse to the touch display array through the sleep driving circuit during a touch sensing period.

Abstract: A pixel circuit includes a liquid crystal capacitor, a memory circuit, a driving circuit, a mode-switching circuit, and a control circuit. The memory circuit is configured to store a status signal. The driving circuit includes a first terminal configured to receive a data voltage and a second terminal electrically coupled to a first terminal of the liquid crystal capacitor, and the driving circuit is configured to be ON or OFF according to a scan signal selectively. The mode-switching circuit is configured to be ON or OFF according to a mode-switching signal selectively. The control signal is electrically coupled to the mode-switching circuit at a first node, and is configured to control the voltage level of the first node corresponding to the status signal, and output a display voltage to the liquid crystal capacitor via the mode-switching circuit when the mode-switching circuit is ON.

Abstract: A display panel, a gate driver and a control method are disclosed herein. The gate driver includes series-coupled driving stages. One of the driving stages includes an input unit and a shift register circuit. The input unit outputs a shift signal to a control node according to a gate driving signal from the previous driving stage and the gate driving signal from the next driving stage. The shift register circuit is electrically coupled to the control node, and outputs the gate driving signal. During the enabling period of the gate driving signal from the previous driving stage and the enabling period of the gate driving signal from the current driving stage, the shift register circuit keeps the voltage level of the control node being at a first voltage.

Abstract: A shift register has a first switch, a pull-up circuit, and a pull-down circuit. The first switch receives a first clock signal. The pull-up circuit is configured to turn on the first switch to pull up a voltage level of an output terminal of the shift register. The pull-up circuit has a second switch and a first control circuit. The first control circuit is coupled to a first system power terminal to avoid an excessive voltage difference between two nodes of the first control circuit. The pull-down circuit is configured to pull down the voltage level of the output terminal of the shift register when the first switch is turned off, and further configured to keep a voltage level of a control node of a switch coupled between the output terminal and a second system power terminal at a low voltage.

Abstract: A shift register has an input stage circuit, a first switch, a control circuit and a pull down circuit. A first end of the first switch receives a first clock signal. A second end and a control end of the first switch are respectively coupled to an output end of the shift register and a first output end of the input stage circuit. The control circuit controls electrical connection between a first power terminal and a node according to a second clock signal and controls electrical connection between the node and a second power terminal according to a voltage level of a second output end of the input stage circuit. The pull down circuit controls electrical connection between the second output end and the second power terminal and electrical connection between the output end and the second power terminal according to a voltage level of the node.

Abstract: A shift register and flat panel display using the same is provided therein. The shift register receives an operating voltage level. Through the circuit provided by the shift register, a driving voltage of an output-stage transistor is higher than prior art. Thus, the shift register has an enhanced driving ability.

Abstract: A liquid crystal display panel includes a pixel array, a first shift register, M first output cells, a second shift register, and N second output cells. The first register is disposed on a first side of the pixel array. The M first output cells are coupled to and next to the first shift register for providing M gate signals to M rows of the pixel array according to a first clock signal. The second register is disposed on a second side of the pixel array. The N second output cells are coupled to and next to the second shift register for providing N gate signals to N rows of the pixel array according to a second clock signal. M and N are positive integers.

Abstract: A shift register and flat panel display using the same is provided therein. The shift register receives an operating voltage level. Through the circuit provided by the shift register, a driving voltage of an output-stage transistor is higher than prior art. Thus, the shift register has an enhanced driving ability.

Abstract: A display panel, a gate driver and a control method are disclosed herein. The gate driver includes series-coupled driving stages. One of the driving stages includes an input unit and a shift register circuit. The input unit outputs a shift signal to a control node according to a gate driving signal from the previous driving stage and the gate driving signal from the next driving stage. The shift register circuit is electrically coupled to the control node, and outputs the gate driving signal. During the enabling period of the gate driving signal from the previous driving stage and the enabling period of the gate driving signal from the current driving stage, the shift register circuit keeps the voltage level of the control node being at a first voltage.

Abstract: A shift register has a first switch, a pull-up circuit, and a pull-down circuit. The first switch receives a first clock signal. The pull-up circuit is configured to turn on the first switch to pull up a voltage level of an output terminal of the shift register. The pull-up circuit has a second switch and a first control circuit. The first control circuit is coupled to a first system power terminal to avoid an excessive voltage difference between two nodes of the first control circuit. The pull-down circuit is configured to pull down the voltage level of the output terminal of the shift register when the first switch is turned off, and further configured to keep a voltage level of a control node of a switch coupled between the output terminal and a second system power terminal at a low voltage.

Abstract: A shift register has an input stage circuit, a first switch, a control circuit and a pull down circuit. A first end of the first switch receives a first clock signal. A second end and a control end of the first switch are respectively coupled to an output end of the shift register and a first output end of the input stage circuit. The control circuit controls electrical connection between a first power terminal and a node according to a second clock signal and controls electrical connection between the node and a second power terminal according to a voltage level of a second output end of the input stage circuit. The pull down circuit controls electrical connection between the second output end and the second power terminal and electrical connection between the output end and the second power terminal according to a voltage level of the node.