Abstract: A method of fabricating a passivation layer is provided. A substrate with a plurality of device structures and at least an interconnect thereon is provided. A patterned metallic layer is formed over the interconnection layer. A plasma-enhanced chemical vapor deposition process is performed to form a first passivation over the metallic layer such that the processing pressure is higher (and/or the processing power is lower) than the pressure (the power) used in prior art. A moisture impermeable second passivation is formed over the first passivation layer. With the first passivation formed in a higher processing pressure (and/or lower processing power), damages to metallic layers or devices due to plasma bombardment is minimized.

Abstract: A method of fabricating a passivation layer is provided. A substrate with a plurality of device structures and at least an interconnect thereon is provided. A patterned metallic layer is formed over the interconnection layer. A plasma-enhanced chemical vapor deposition process is performed to form a first passivation over the metallic layer such that the processing pressure is higher (and/or the processing power is lower) than the pressure (the power) used in prior art. A moisture impermeable second passivation is formed over the first passivation layer. With the first passivation formed in a higher processing pressure (and/or lower processing power), damages to metallic layers or devices due to plasma bombardment is minimized.

Abstract: A dual damascene process for producing interconnects. A dielectric layer is formed over the surface of a semiconductor substrate which comprises conductive layers or MOS devices. The dielectric layer is patterned to form trench openings and a metal layer is deposited over the dielectric layer to fill the plurality of trenches. A photoresist layer is formed over the metal layer and defined to form via hole patterns above the trenches. The metal layer and the dielectric layer are etched with the patterned photoresist layer as a mask to form a plurality of via holes exposing the underlying conductive layer or MOS devices and a dual damascene opening is formed.

Abstract: The present invention provides a process for preparing a molybdenum, molybdenum silicide or molybdenum carbide/ceramic admixture, comprising dissolving molybdenum trioxide powder with an alkaline solvent to obtain an aqueous solution of molybdate; incorporating ceramic powder with or without silicon and/or carbon powder into the aqueous solution of molybdate to obtain a slurry; and subjecting the slurry to spray drying and reduction to obtain the admixture. The obtained admixture can be formed and sintered into a nanometer-sized and uniformly dispersed molybdenum, molybdenum silicide or molybdenum carbide/ceramic sintered composites.