Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: Disclosed is a method of fabricating carbon nanotubes and carbon nano particles, the method comprising: providing a plurality of carbon micro carriers on a silicon substrate; forming a plurality of carbon nano particles on the carbon micro carrier by a first gas; and reacting with a second gas to provide a plurality of carbon nanotubes. Thus the carbon nanotube can be formed without the use of a metal catalyst. The carbon nanotubes can easily separate from each other without the problem of non-uniformity, because the carbon micro carrier used is in a microscale size.

Abstract: An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A. An input buffer is connected between the HV terminal and the ground terminal and has an input terminal connected to a DATA INPUT terminal. An output terminal of the input buffer is connected to the latch input node B. The input buffer is enabled during a load-data mode of operation to load data from a DATA INPUT terminal to the latch input node B of the cross-coupled high-voltage CMOS latch.

Abstract: A circuit for eliminating pop sounds at power on and off by a moderate waveform, which includes a switch, a feedback network, an operational amplifier and an output network. When power-on, a first input terminal of the switch is connected to a low voltage, and an output terminal of the output network provides an operating DC bias which is gradually increased. When power-off, the first input terminal of the switch is connected to a reference voltage, and the output terminal of the output network provides an operating DC bias which is gradually reduced.

Abstract: An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A. An input buffer is connected between the HV terminal and the ground terminal and has an input terminal connected to a DATA INPUT terminal. An output terminal of the input buffer is connected to the latch input node B. The input buffer is enabled during a load-data mode of operation to load data from a DATA INPUT terminal to the latch input node B of the cross-coupled high-voltage CMOS latch.

Abstract: An improved CMOS high-voltage latch stores data bits to be written to memory cells of a non-volatile memory has two cross-coupled CMOS inverters. One of the inverters has a pull-down leg that includes a pass-gate high-voltage NMOS transistor that is connected between a latch output node and a second high-voltage, low-threshold NMOS pull-down transistor that is connected to ground. A gate of the pass-gate high-voltage NMOS transistor receives a standby signal with a logic HIGH value of at most Vdd to turn on the pass-gate high-voltage NMOS transistor when the high-voltage CMOS latch is in a voltage mode of operation and during a high-voltage write mode of operation. The pass-gate high-voltage NMOS transistor thereby limits the voltage across the second high-voltage, low-threshold NMOS pull-down transistor to less than the standby signal in order to reduce punch-trough current and drain-to-substrate leakage of the second high-voltage, low-threshold NMOS pull-down transistor.

Abstract: A power down reset circuit for asserting a signal when a first VDD voltage falls below a voltage threshold. The circuit has at least one diode coupled to the first VDD voltage. The at least one diode is configured to produce a second voltage. At least one capacitor is coupled to the at least one diode to maintain the second voltage. A voltage detector asserts a signal when the first VDD voltage drops below a threshold level. The voltage detector is powered by the second voltage and is coupled to the at least one diode.

Abstract: An exemplary liquid crystal display (LCD) (100) includes a liquid crystal panel (12) comprising a plurality of scanning lines; a light guide plate (10) under the liquid crystal panel; and a light source (13) adjacent to a side of the light guide plate. The light source has a plurality of light emitting diodes, which turn on or turn off according to the different system displaying mode.

Abstract: An exemplary method for manufacturing a color filter, comprising the steps of: providing a substrate; forming a black matrix on the substrate; forming a photo-resist layer on the substrate; and continuously exposing the photo-resist layer using at least three light sources respectively having different wavelengths and developing the photo-resist layer to form color photo-resist layer.

Abstract: An exemplary liquid crystal display (200) has a liquid crystal panel (240); a gate driving circuit (230) configured for scanning the liquid crystal panel; a data driving circuit (220) configured for providing a plurality of gradation voltages to the liquid crystal panel; a photo sensor (241) configured for measuring a luminance of ambient light and generating a corresponding optical signal; a luminance control circuit (231) for receiving the optical signal from the photo sensor and transferring the optical signal to a measurement signal; a timing control circuit (210) configured for controlling the gate driving circuit and the data driving circuit; and a backlight circuit (270) for driving a light source to emit light beams for illuminating the liquid crystal panel, according to the measurement signal from the luminance control circuit.

Abstract: An exemplary liquid crystal display (LCD) has a first substrate (22), which has a first positional mark (224) having a first horizontal positional sub-mark (225) and a first vertical positional sub-mark (227), perpendicular to each other; a second substrate (24), which has a second positional mark (243) having a second horizontal positional sub-mark (245) and a second vertical positional sub-mark (247), perpendicular to each other. The first and the second horizontal positional marks correspond to each other, which each have a plurality of periodically distributed parallel lines; the first and the second vertical positional marks correspond to each other, which each have a plurality of vertical distributed parallel lines. When the first and the second substrate are assembled, the lines of the first and the second horizontal or vertical positional marks cross each other to form morie fringes.

Abstract: An exemplary backlight module and a liquid crystal display device using the backlight module are provided. The backlight module includes a light beam generator and a reflector. The light beam generator includes a light source, a polygon mirror and an f-theta lens. The polygon mirror reflects light beams into a scanning light beam which can rotate at a certain speed. The scanning light beam transmits through the f-theta lens, and then it is transferred into parallel scanning beams. The parallel scanning beams reach the reflector. A light source device to produce a scanning light beam is also provided. The light source device can improve the uniformity of emission of the backlight module.

Abstract: An exemplary light guide plate (14) includes a light incident surface (140), a light emitting surface (142) adjacent the light incident surface, a bottom surface (144) opposite to the light emitting surface, and a plurality of side surfaces (146, 148) between the light emitting surface and the bottom surface. At least one dammann grating structure (149) is provided at at least one of the bottom surface and the side surfaces.

Abstract: A flash memory programming process incorporates two charge pumps per byte of bit cells. Placing a data “one” value in each bit cell erases an entire memory device. Before programming each cell, a prospective data content is scrutinized. If a data “zero” is to be applied to the bit cell, a charge pump engages to bias the cell and activate a hot electron injection process to affect the programming. If a data “one” is to be applied to the bit cell, no programming activity is undertaken and the process increments to the next bit cell in the data structure. Therefore, total programming time is reduced proportionally to the number of data “one” bits to be programmed. Where more than one charge pump is engaged in parallel to a data structure, total programming time is further reduced when two data “one” values are to be programmed in parallel.

Abstract: An exemplary backlight module (2) includes a metal frame (27), and a light source (21). The metal frame includes inner side and a containing space. The light source is received in the containing space. The inner side includes microstructures (271) configured to optimize absorption of heat thereat.

Abstract: An exemplary alignment apparatus (2) includes a light source (50) for emitting light (501), a polarized light generator (51) for receiving the light and generating polarized light (504), a polarized light separator (52) for receiving the polarized light and separating the polarized light into a reflection polarized light beam (521) and a transmission polarized light beam (522) having capability to interfere with each other, a light reflector for changing transmission directions of the reflection and transmission polarized light beams to make the reflection and transmission polarized light beams parallel to each other, and a convergent lens (53) for making the reflection and transmission polarized light beams converge and interferingly irradiate a photosensitive polymer layer (30) to obtain an alignment layer (60). Unlike with conventional alignment apparatuses, because the alignment apparatus is no-rubbing, no-contact alignment apparatuses, debris and electrostatic charge are avoided or even eliminated.

Abstract: A backlight module (3) includes a light guide plate (31), a light source (32) and an optical conversion device (33). The light guide plate includes an incident surface (311), an emitting surface (312) adjacent to the incident surface and a bottom surface (313) parallel to the emitting surface. The incident surface maintains an oblique angle relative to the bottom surface. The light source is near the incident surface of the light guide plate for radiating light beams toward the light guide plate. The optical conversion device is disposed between the light source and the light incident surface, which is configured for transforming a polarization state of some of the light beams received from the light source such that the transformed light beams can enter the light guide plate through the incident surface.

Abstract: A dual display structure has a back light module, a first display panel deposited on one side of the back light module, a housing for putting and fixing the back light module and the first display panel, and a second display panel. The housing has a firm plate having a light exit opening. The back light module is disposed on a first firm surface of the firm plate, and the first firm surface has a gray face for absorbing the emitted light from the back light module that can make uniform light of the whole back light module. The second display panel is disposed on a second firm surface of the firm plate, and the back light module provides light through the light exit opening to the second display panel.

Abstract: A backlight module (10) includes a light guide plate (100) and a light source (110). The light guide plate includes a light incident surface (102). The light incident surface includes a plurality of dots (108) provided thereat. The light source is disposed adjacent to the light incident surface. A sum of a size of one dot and a pitch between adjacent dots is less than 380 nm. The backlight module can obtain optimized optical performance.