Abstract: Disclosed is a light-emitting diode display module, including a first light-emitting diode, a second light-emitting diode, a third light-emitting diode, a scan block, a voltage conversion block, a first sink block, and a second sink block. An operating voltage of the first light-emitting diode is lower than that of the second and third light-emitting diodes. The voltage conversion block provides an auxiliary power supply voltage based on a high power supply voltage and a low power supply voltage. The first light-emitting diode is coupled between the scan block and the first sink block receiving the high power supply voltage and the auxiliary power supply voltage. The second light-emitting diode and the third light-emitting diode are coupled between the scan block and the second sink block receiving the high power supply voltage and the low power supply voltage.

Abstract: Disclosed is a light-emitting diode display module, including a first light-emitting diode, a second light-emitting diode, a third light-emitting diode, a scan block, a voltage conversion block, a first sink block, and a second sink block. An operating voltage of the first light-emitting diode is lower than that of the second and third light-emitting diodes. The voltage conversion block provides an auxiliary power supply voltage based on a high power supply voltage and a low power supply voltage. The first light-emitting diode is coupled between the scan block and the first sink block receiving the high power supply voltage and the auxiliary power supply voltage. The second light-emitting diode and the third light-emitting diode are coupled between the scan block and the second sink block receiving the high power supply voltage and the low power supply voltage.

Abstract: The present disclosure provides a display device, including first to fourth LEDs, a line structure, and first to fourth lines. The second LED is arranged in a first direction corresponding to the first LED. The fourth LED is arranged in a second direction corresponding to the third LED. The line structure includes first to third line segments. The first line is coupled to the first LED. The second line is coupled to the second LED. The third line is coupled to the third LED. The fourth line is coupled to the fourth LED. A portion of the first line and a portion of the second line are in parallel with the first line segment, a portion of the third line is in parallel with the second line segment, and a portion of the fourth line is in parallel with the third line segment.

Abstract: A driving device comprises a first complementary metal-oxygen-semiconductor circuit and a first comparator. The first complementary metal-oxygen-semiconductor circuit is configured for outputting a power signal or a pull-down signal according to the first input signal. The first comparator comprises a first non-inverting input terminal and a first inverting input terminal. The first non-inverting input terminal is coupled to the first complementary metal-oxygen-semiconductor circuit, and is configured to receive the power signal or the pull-down signal. The first inverting input terminal is configured for receiving a first reference signal, and the first comparator is configured to compare one of the power signal and the pull-down signal and the first reference signal to provide a first driving signal.

Abstract: The present disclosure provides a driving circuit, including a transistor and a level shifter. The first terminal of the transistor is electrically connected to a light emitting diode and is configured to receive a supply voltage. The second terminal of the transistor is configured to receive a first reference voltage. The level shifter is configured to receive an input signal from a previous-stage driving circuit and adjust the voltage level of the input signal according to a voltage operating range formed by the supply voltage and the first reference voltage to generate a level-shifted signal corresponding to the voltage operating range and configured to control the transistor. The input signal varies between a second reference voltage and the supply voltage. The second reference voltage and the first reference voltage are different from each other and both lower than the supply voltage.

Abstract: In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

Abstract: In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

Abstract: In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

Abstract: A source driving system includes first and second source driving integrated circuits. The first driving integrated circuit includes a first source driver for receiving first display data and driving pixels in a first block of a display panel according to the first display data. The second source driving integrated circuit includes a second source driver electrically connected to the first source driver for receiving second display data and driving pixels in a second block of the display panel according to the second display data. The first and the second source drivers generate first and second display parameters according to the first and the second display data respectively. The second display parameter is transmitted from the second source driver to the first source driver. The first source driver generates a third display parameter according to the first and second parameters and transmits the third display parameter to the second source driver.

Abstract: In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

Abstract: A driving circuit includes a power supply, a plurality of conductive paths and a plurality of driving controller. The power supply is configured for providing a predetermined voltage. The conductive paths are connected to the power supply to receive the predetermined voltage. The driving controllers are connected to the conductive paths correspondingly. A first driving controller of the driving controllers has a first internal circuit configured for employing an internal voltage to perform functions provided by the first driving controller, and a resistance adjustment unit. The resistance adjustment unit is connected between a special conductive path and the first internal circuit. The second driving controller has a second internal circuit configured for employing a second internal voltage to perform functions provided by the second driving controller. A resistance value of the resistance adjustment unit is adjustable to make the first internal voltage same to the second internal voltage.

Abstract: A driving apparatus for a liquid crystal display (LCD) is provided. The driving apparatus includes a plurality of data driving ICs and a control board. The data driving ICs are used for receiving and transmitting a clock signal, a plurality of data signals and a first reference voltage from the 1st data driving IC to the last data driving IC in series. The control board is used for providing the clock signal, the data signals and the first reference voltage, and changing the first reference voltage received by each data driving IC according to a variation of the clock signal and the data signals transmitted between the data driving ICs, so that the operation frequency of the data driving ICs is unrestricted.

Abstract: A control signal generation method of integrated gate driver circuit includes the steps of: providing one gate control signal to an integrated gate driver circuit; and generating a plurality of internal control signals by the integrated gate driver circuit according to on the gate control signal to control internal operations of the integrated gate driver circuit. Furthermore, an integrated gate driver circuit is adapted to receive one external gate control signal. The integrated gate driver circuit includes an internal control signal generation circuit for generating a plurality of internal control signals according to the external gate control signal to control internal operations of the integrated gate driver circuit. In addition, a liquid crystal display device using the above-mentioned integrated gate driver circuit also is provided.

Abstract: A driving circuit includes a power supply, a plurality of conductive paths and a plurality of driving controller. The power supply is configured for providing a predetermined voltage. The conductive paths are connected to the power supply to receive the predetermined voltage. The driving controllers are connected to the conductive paths correspondingly. A first driving controller of the driving controllers has a first internal circuit configured for employing an internal voltage to perform functions provided by the first driving controller, and a resistance adjustment unit. The resistance adjustment unit is connected between a special conductive path and the first internal circuit. The second driving controller has a second internal circuit configured for employing a second internal voltage to perform functions provided by the second driving controller. A resistance value of the resistance adjustment unit is adjustable to make the first internal voltage same to the second internal voltage.

Abstract: A driving apparatus for a liquid crystal display (LCD) is provided. The driving apparatus includes a plurality of data driving ICs and a control board. The data driving ICs are used for receiving and transmitting a clock signal, a plurality of data signals and a first reference voltage from the 1st data driving IC to the last data driving IC in series. The control board is used for providing the clock signal, the data signals and the first reference voltage, and changing the first reference voltage received by each data driving IC according to a variation of the clock signal and the data signals transmitted between the data driving ICs, so that the operation frequency of the data driving ICs is unrestricted.

Abstract: A data driver using a gamma selecting signal, a flat panel display with the same and a driving method therefor are provided. A first to a fourth data lines are electrically connected to a first left sub-pixel, a first right sub-pixel, a second right sub-pixel and a second left sub-pixel, respectively. The data driver includes a first, a second, a third and a fourth gray level generating units for outputting a first set of positive gray voltage, a second set of negative gray voltage, a second set of positive gray voltage and a first set of negative gray voltage, respectively. The data driver drivers these sub-pixels according to the first set of positive gray voltage, the second set of negative gray voltage, the second set of positive gray voltage and the first set of negative gray voltage under the control of a polarity inversion signal and a gamma selecting signal.

Abstract: A drive circuit includes a drive unit coupling with data lines for receiving at least one clock signal and a first enable signal to generate a drive signal to drive data lines, and a delay unit electrically coupled with the drive unit for receiving the clock signal and the first enable signal and generating a second enable signal falling subsequent to the first enable signal in a predetermined time interval.

Abstract: A panel circuit structure for transmitting electrical signals to an active area is provided. The panel circuit structure includes a first transmission pad, a first test pad, a second transmission pad, a second test pad, and a third transmission pad, which are connected to a driving element. The first transmission pad, the first test pad, the second transmission pad, and the second test pad transmit electrical signals to the active area via the first transmission lines and second transmission lines. The first transmission pads and the second transmission pads are disposed at a first end of the driving element while the third transmission pad is disposed at a second end of the driving element. The first and second test pads are disposed outside the coverage area of the driving element.

Abstract: A shift register applied on a double-frame-rate LCD is provided. The LCD includes an upper display area with c gate lines, a lower display area with d gate lines, and a gate driving circuit. The gate driving circuit includes a first shift register coupled to the corresponding x gate lines of the upper display area, a second shift register coupled to the corresponding y lines of the lower display area, and a third shift register coupled to the corresponding (c-x) gate lines of the upper display area and the corresponding (d-y) gate lines of the lower display area.

Abstract: A control signal generation method of integrated gate driver circuit includes the steps of: providing one gate control signal to an integrated gate driver circuit; and generating a plurality of internal control signals by the integrated gate driver circuit according to on the gate control signal to control internal operations of the integrated gate driver circuit. Furthermore, an integrated gate driver circuit is adapted to receive one external gate control signal. The integrated gate driver circuit includes an internal control signal generation circuit for generating a plurality of internal control signals according to the external gate control signal to control internal operations of the integrated gate driver circuit. In addition, a liquid crystal display device using the above-mentioned integrated gate driver circuit also is provided.