Abstract: A semiconductor device includes a capacitor structure that includes an insulator layer stack with a plurality of aluminum oxide layers and a plurality of zirconium oxide layers. The insulator layer stack is formed on a bottom electrode layer of the capacitor structure. The arrangement of the aluminum oxide layers at a bottom and a top of the insulator layer stack prevents oxygen migration from the zirconium oxide layers to the electrode layers of the capacitor structure, while achieving higher capacitance levels than those of capacitor structures with differently arranged insulator layers. In addition, since the aluminum oxide layers of the insulator layer stack prevent oxygen migration from the zirconium oxide layers of the insulator layer stack to the electrode layers of the capacitor structure, faster discharge times can be achieved for the capacitor structure.

Abstract: Provided are a 3D memory and an operating method thereof. In the 3D memory, a stacked structure includes gate layers and insulating layers alternately stacked. Each gate layer includes first and second gates spaced from each other. Each annular channel layer corresponds to one of the gate layers and is disposed between adjacent insulating layers. A p-type doping region is disposed in each channel layer and adjacent to the first gate. An n-type doped region is disposed in each channel layer and adjacent to the second gate. A source line pillar penetrates through the stacked structure and contacts the n-type doped region. A bit line pillar penetrates through the stack structure and contacts the p-type doped region. A first gate insulation layer is disposed between the first gate and the channel layer. A second gate insulation layer is disposed between the second gate and the channel layer.

Abstract: Provided are a 3D memory and an operating method thereof. In the 3D memory, a stacked structure includes gate layers and insulating layers alternately stacked. Each gate layer includes first and second gates spaced from each other. Each annular channel layer corresponds to one of the gate layers and is disposed between adjacent insulating layers. A p-type doping region is disposed in each channel layer and adjacent to the first gate. An n-type doped region is disposed in each channel layer and adjacent to the second gate. A source line pillar penetrates through the stacked structure and contacts the n-type doped region. A bit line pillar penetrates through the stack structure and contacts the p-type doped region. A first gate insulation layer is disposed between the first gate and the channel layer. A second gate insulation layer is disposed between the second gate and the channel layer.

Abstract: A key generation technology of the present disclosure does not additionally set a combinational logic circuit on an original path of a scanning flip-flop, but utilizes a plurality of existing combinational logic circuits in a circuit system to generate multiple values of a key. Correspondingly, a key generation unit used in the key generation technology has two data flip-flops. One of the data flip-flops is used as a data flip-flop in one of a plurality of scanning flip-flops. The other data flip-flop is to obtain a node data signal of a node in the corresponding combinational logic circuit as one of the values of the key.

Abstract: A metallic ferroelectric metal (MFM) field effect transistor (FET) is provided that includes an MFM, a first FET and a second FET. The MFM has a first electrode. The first FET is electrically connected to the first electrode, and has a first gate electrode, wherein the first gate electrode has a first area. The second FET is electrically connected to the first electrode, and has a second gate electrode, wherein the second gate electrode has a second area, and the first area and the second area have a ratio therebetween ranging from 1:50 to 1:2.

Abstract: An embodiment of the invention provides a data authentication device. The data authentication device may include a main memory, a backup memory, a platform control hub (PCH) and an embedded controller (EC). The main memory may be configured to store data. The backup memory may be configured to back up the data stored in the main memory. The PCH is coupled to the main memory and generates a write command to write a first data image to the main memory, wherein the first data image comprises updated data and a digital signature. The EC is coupled to the main memory, the backup memory and the PCH and obtains the first data image from the PCH. When the EC detects a write command, the EC may perform an authentication for the updated data based on the first data image or a second data image corresponding to the first data image.

Abstract: A metallic ferroelectric metal (MFM) field effect transistor (FET) is disclosed. The metallic ferroelectric metal (MFM) field effect transistor (FET) includes an MFM, a first FET and a second FET. The MFM has a first electrode. The first FET is electrically connected to the first electrode, and has a first gate electrode, wherein the first gate electrode has a first area. The second FET is electrically connected to the first electrode, and has a second gate electrode, wherein the second gate electrode has a second area, and the first area and the second area have a ratio therebetween ranging from 1:50 to 1:2.

Abstract: A key generation technology of the present disclosure does not additionally set a combinational logic circuit on an original path of a scanning flip-flop, but utilizes a plurality of existing combinational logic circuits in a circuit system to generate multiple values of a key. Correspondingly, a key generation unit used in the key generation technology has two data flip-flops. One of the data flip-flops is used as a data flip-flop in one of a plurality of scanning flip-flops. The other data flip-flop is to obtain a node data signal of a node in the corresponding combinational logic circuit as one of the values of the key.

Abstract: A sensor is provided, including a substrate, a chip and a sensing element. The substrate has a plate-like shape and includes a surface and an interconnect structure disposed in the substrate. The chip is embedded in the substrate and is electrically connected to the interconnect structure. The sensing element is disposed on the surface of the substrate, and is electrically connected to the chip through the interconnect structure.

Abstract: A cascade extension device and a cascade system having the cascade extension device are provided. The cascade extension device includes a control module, a buffer module, a storage module, and a selecting output module. The cascade system includes a processor and a plurality of extension devices. The processor may simultaneously control the plurality of extension devices through judging the data packet received as a write command, a read command, or a bypass command by a plurality of extension devices.

Abstract: A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.

Abstract: A photosensitive module is provided. The photosensitive module includes a base, an integrated package substrate, and a photosensitive element. The integrated package substrate is connected to the base. The integrated package substrate has a plurality of first electronic components, and the first electronic components are housed inside the integrated package substrate without being exposed to external environment. The photosensitive element is connected to the base, and the photosensitive element is configured to receive a light beam traveling along an optical axis.

Abstract: A photosensitive module is provided. The photosensitive module includes a base, an integrated package substrate, and a photosensitive element. The integrated package substrate is connected to the base. The integrated package substrate has a plurality of first electronic components, and the first electronic components are housed inside the integrated package substrate without being exposed to external environment. The photosensitive element is connected to the integrated package substrate, and the photosensitive element is configured to receive a light beam traveling along an optical axis.

Abstract: A cascade extension device and a cascade system having the cascade extension device are provided. The cascade extension device includes a control module, a buffer module, a storage module, and a selecting output module. The cascade system includes a processor and a plurality of extension devices. The processor may simultaneously control the plurality of extension devices through judging the data packet received as a write command, a read command, or a bypass command by a plurality of extension devices.

Abstract: A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.

Abstract: A package structure is provided, including a first insulating layer, a second insulating layer, a third insulating layer, and a chip. The second insulating layer is disposed on the first insulating layer, the chip is disposed in the second insulating layer, and the third insulating layer is disposed on the second insulating layer. The heat conductivity of the second insulating layer is lower than the heat conductivity of the first insulating layer, and the hardness of the second insulating layer is lower than the hardness of the first insulating layer.

Abstract: An integrated circuit (IC) is provided. The IC includes a specific pin, a pull-down circuit and a voltage detector coupled to the specific pin, and a controller. The pull-down circuit includes a pull-down resistor corresponding to a driving voltage level, and is configured to selectively couple the pull-down resistor to the specific pin according to a control signal. The voltage detector is configured to detect the specific pin to obtain a detected voltage value. The controller is configured to determine whether the detected voltage value is the same as the driving voltage level, so as to provide the control signal. When the detected voltage value is greater or less than the driving voltage level, the controller is configured to provide the control signal to the pull-down circuit, so that the pull-down resistor is electrically separated from the specific pin.

Abstract: A photosensitive module is provided. The photosensitive module includes a base, an integrated package substrate, and a photosensitive element. The integrated package substrate is connected to the base. The integrated package substrate has a plurality of first electronic components, and the first electronic components are housed inside the integrated package substrate without being exposed to external environment. The photosensitive element is connected to the integrated package substrate, and the photosensitive element is configured to receive a light beam traveling along an optical axis.

Abstract: A photosensitive module is provided. The photosensitive module includes a base, an integrated package substrate, and a photosensitive element. The integrated package substrate is connected to the base. The integrated package substrate has a plurality of first electronic components, and the first electronic components are housed inside the integrated package substrate without being exposed to external environment. The photosensitive element is connected to the base, and the photosensitive element is configured to receive a light beam traveling along an optical axis.

Abstract: A substrate structure is provided, including a substrate, an integrated circuit chip, a circuit structure, and a thermal-dissipating structure. The integrated circuit chip is disposed in the substrate. The circuit structure is electrically connected to the integrated circuit chip. The thermal-dissipating structure is disposed in the substrate and adjacent to the integrated circuit chip, and the thermal-dissipating structure is electrically isolated from the circuit structure.