Abstract: An embodiment of the instant invention is a method of oxidizing a first feature (feature 108 and/or feature 104 of FIG. 1 and feature 314 of FIG. 3) while leaving a second feature substantially unoxidized (features 110 and 112 of FIG. 1 and features 310 and 312 of FIG. 3), the method comprised of subjecting the first and second features to an oxygen-containing gas and a separate hydrogen-containing gas. Preferably, the oxygen-containing gas is comprised of gas selected from the group consisting of O2, N2O, CO2, H2O, and any combination thereof, and the hydrogen-containing gas is comprised of H2. The first feature is, preferably, comprised of polycrystalline silicon, silicon oxide, or a dielectric material, and the second feature is, preferably, comprised of tungsten.

Abstract: A method of forming an ultra-thin gate oxide (14) for a field effect transistor (10). The gate oxide (14) is formed by combining an oxidizing agent (e.g., N2O, CO2) with an etching agent (e.g., H2) and adjusting the partial pressures to controllably grow a thin (˜12 Angstroms) high quality oxide (14).

Abstract: A method of forming an ultra-thin gate oxide (14) for a field effect transistor (10). The gate oxide (14) is formed by combining an oxidizing agent (e.g., N2O, CO2) with an etching agent (e.g., H2) and adjusting the partial pressures to controllably grow a thin (˜12 Angstroms) high quality oxide (14).

Abstract: A method for protecting metal (112) from oxidation during various oxidation steps such as CVD SiO2 oxidation for forming an overlying oxide layer (114), smile oxidation, and sidewall (116) deposition. The gas CO2 is added to the oxidation chemistry. The CO2/H2 ratio is controlled for selective oxidation. The metal (112) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagents.

Abstract: A thermal neutron shield (520) for integrated circuits (511-515) deters absorption of thermal neutrons by circuit constituents to form unstable isotopes with subsequent decay which generates bursts of charge which may upset of stored charge and create soft errors. The shielding may be either at the integrated circuit level (such as a layer on insulation or in the filler of plastic packaging material) or at the board level (such as a filler or film on a container wall).

Abstract: A method and apparatus for selectively heating a structure capable of absorbing heat radiations in the 0.5 to 2 micron range relative to an adjacent structure wherein a first structure capable of absorbing heat radiations in the 0.5 to 2 micron range is disposed adjacent a second structure much less capable of absorbing heat radiations in the 0.5 to 2 micron range. An unfocused heat source which provides a major portion of its heat energy in the range of from about 0.5&mgr; to about 2&mgr; relative to heat energy above 2&mgr; and below 0.5 micron directs heat concurrently to the first and second structures to heat the first structure to a temperature sufficiently high and much higher then the second structure to permit a predetermined function to be performed in conjunction with the first structure while maintaining the second structure below a predetermined temperature. The function is then performed. The heat source preferably comprises an unfocused tungsten halogen lamp.

Abstract: A method of forming an ultra-thin gate oxide (14) for a field effect transistor (10). The gate oxide (14) is formed by combining an oxidizing agent (e.g., N2O, CO2) with an etching agent (e.g., H2) and adjusting the partial pressures to controllably grow a thin (˜12 Angstroms) high quality oxide (14).

Abstract: A cost-effective method for fabricating MIM capacitors (120). After metal (106) deposition, the metal oxide (108) is formed using an oxidation chemistry that includes CO2 and H2. The CO2/H2 gas ratio is controlled for selective oxidation. Thus, the metal (106) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagent.

Abstract: A process for forming a W-poly gate stack (110) comprising the steps of: (1) deposition of doped polysilicon (112) on a thin dielectric layer (108) covered substrate (102), (2) deposition of WNx by a CVD-based process, (3) thermal treatment to covert WNx into thermally stable barrier, WSiNx, (114) and to remove excess nitrogen and (4) deposition of W layer (116). The stack layers are then etched to form the gate electrode (110).

Abstract: A method for fabricating a low resistivity polymetal silicide conductor/gate comprising, the steps of forming a polysilicon (66) over a gate oxide (64) followed by protection of the polysilicon (66) with a sacrificial material (68), is disclosed. Gate sidewalls (70) are created to protect the sides of the polysilicon (66) and the sacrificial material (68), followed by stripped the sacrificial material (68) to expose the top surface of the polysilicon (66). Next, a diffusion barrier (76) is deposited over the exposed polysilicon (66) and a metal layer (78) is selectively grown on the diffusion barrier (76) to form a gate contact and conductor. Finally, a dielectric layer (80) is deposited over the selectively grown metal layer (78), the sidewalls (70) and the gate oxide (64).

Abstract: A metal-poly stack gate structure and associated method for forming a conductive barrier layer between W and poly in the metal-gate stack gate structure. The process includes the steps of depositing doped silicon on a substrate; forming nitride on the deposited silicon; depositing a metal on the nitride to form a metal/nitride/deposited silicon stack; and thermally treating the stack to transform the nitride into a conductive barrier layer between the metal and the deposited silicon. The thermal treatment transforms the nitride layer (SiN.sub.x or SiN.sub.x O.sub.y) into a conductive barrier (WSi.sub.x N.sub.y or WSi.sub.x N.sub.y O.sub.z) to form a W/barrier/poly stack gate structure. The barrier layer blocks reaction between W and Si, enhances sheet resistance, enhances adhesion between the W and the poly, and is stable at high temperatures.

Abstract: A method and apparatus for selectively heating a structure (20) capable of absorbing heat radiations in the 0.5 to 2 micron range relative to an adjacent structure (24) wherein a first structure capable of absorbing heat radiations in the 0.5 to 2 micron range is disposed adjacent a second structure much less capable of absorbing heat radiations in the 0.5 to 2 micron range. An unfocused heat source (28) which provides a major portion of its heat energy in the range of from about 0.5.mu. to about 2.mu. relative to heat energy above 2.mu. and below 0.5 micron directs heat concurrently to the first and second structures to heat the first structure to a temperature sufficiently high and much higher then the second structure to permit a predetermined function to be performed in conjunction with the first structure while maintaining the second structure below a predetermined temperature. The function is then performed. The heat source preferably comprises an unfocused tungsten halogen lamp.

Abstract: In semiconductor device assembly operations, the use of an optical heat source 28, such as a tungsten halogen lamp module, is to replace ovens and heater blocks for curing die-attach material and molding compound with reduction in cycle time, cost, footprint, and contamination.

Abstract: Semiconductor die attach occurs by bonding the semiconductor die to a support member such as a lead frame. An optical heat source provides heat for bonding the die attach material. An exhaust system removes vapors from the die attach material during bonding. A tungsten halogen lamp is an exemplary optical heat source. An air amplifier is exemplary to provide exhaust pressure. An exhaust manifold having a plurality of screens spreads the exhaust pressure over the width of the lead frame. A gas shower disposed over the lead frame aids in removing vapors.

Abstract: This is a system and method of in-situ coating, baking and curing of dielectric material. The system may include: dispensing apparatus for dispensing spin-on material; a lamp module 50; a window 54 connected to the lamp module 50; an environmental control chamber 56 connected to the window 54; an access gate 60 for wafers 58 in the environmental control chamber 56; a spin chuck 62 inside the environmental control chamber 56; and an exhaust pipe 64 connected to the environmental control chamber 56. The lamp module 50 may contains infra red and ultra violet lamps. In addition, the coating chamber may process dielectric material such as spin-on glass, silicon dioxide and various other spin-on material.

Abstract: A method and apparatus for sensing radiation 26 indicative of at least one process variable in a semiconductor process chamber 10 in which a reactant gas reacts to effect changes in a silicon wafer 12. The method comprises positioning a substantially transparent window 22 in a conduit 14 leading to the wafer 12 and then flowing the reactant gas in the conduit 14 past the window 22 and toward the wafer 12. The radiation 26 is then sensed through the window 22. In the preferred embodiment the window 22 is positioned with an optical path along the center axis of the conduit 14. Other systems and methods are also disclosed.