Patents by Inventor Minghwei Hong

Minghwei Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11615955
    Abstract: A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: March 28, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Bo-Yu Yang, Minghwei Hong, Jueinai Kwo, Yen-Hsun Lin, Keng-Yung Lin, Hsien-Wen Wan, Chao Kai Cheng, Kuan Chieh Lu
  • Publication number: 20230011006
    Abstract: A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.
    Type: Application
    Filed: March 3, 2022
    Publication date: January 12, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Minghwei HONG, Juei-Nai KWO, Tun-Wen PI, Hsien-Wen WAN, Yi-Ting CHENG, Yu-Jie HONG
  • Patent number: 11201055
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, forming a high-? dielectric layer directly on the semiconductor layer as formed, and annealing the semiconductor layer, the high-dielectric layer, and the substrate. The semiconductor layer is a Group III-V compound semiconductor.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: December 14, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chien-Hua Fu, Keng-Yung Lin, Yen-Hsun Lin, Kuanhsiung Chen, Juei-Nai Kwo, Minghwei Hong
  • Patent number: 11081339
    Abstract: A substrate with a (001) orientation is provided. A gallium arsenide (GaAs) layer is epitaxially grown on the substrate. The GaAs layer has a reconstruction surface that is a 4×6 reconstruction surface, a 2×4 reconstruction surface, a 3×2 reconstruction surface, a 2×1 reconstruction surface, or a 4×4 reconstruction surface. Via an atomic layer deposition process, a single-crystal structure yttrium oxide (Y2O3) layer is formed on the reconstruction surface of the GaAs layer. The atomic layer deposition process includes water or ozone gas as an oxygen source precursor and a cyclopentadienyl-type compound as an yttrium source precursor.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuanhsiung Chen, Minghwei Hong, Jueinai Kwo, Yen-Hsun Lin, Keng-Yung Lin
  • Publication number: 20200388490
    Abstract: A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Bo-Yu YANG, Minghwei HONG, Jueinai KWO, Yen-Hsun LIN, Keng-Yung LIN, Hsien-Wen WAN, Chao Kai CHENG, Kuan Chieh LU
  • Patent number: 10755924
    Abstract: A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: August 25, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Bo-Yu Yang, Minghwei Hong, Jueinai Kwo, Yen-Hsun Lin, Keng-Yung Lin, Hsien-Wen Wan, Chao Kai Cheng, Kuan Chieh Lu
  • Publication number: 20190252184
    Abstract: A substrate with a (001) orientation is provided. A gallium arsenide (GaAs) layer is epitaxially grown on the substrate. The GaAs layer has a reconstruction surface that is a 4×6 reconstruction surface, a 2×4 reconstruction surface, a 3×2 reconstruction surface, a 2×1 reconstruction surface, or a 4×4 reconstruction surface. Via an atomic layer deposition process, a single-crystal structure yttrium oxide (Y2O3) layer is formed on the reconstruction surface of the GaAs layer. The atomic layer deposition process includes water or ozone gas as an oxygen source precursor and a cyclopentadienyl-type compound as an yttrium source precursor.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Inventors: Kuanhsiung Chen, Minghwei Hong, Jueinai Kwo, Yen-Hsun Lin, Keng-Yung Lin
  • Patent number: 10283349
    Abstract: A substrate with a (001) orientation is provided. A gallium arsenide (GaAs) layer is epitaxially grown on the substrate. The GaAs layer has a reconstruction surface that is a 4×6 reconstruction surface, a 2×4 reconstruction surface, a 3×2 reconstruction surface, a 2×1 reconstruction surface, or a 4×4 reconstruction surface. Via an atomic layer deposition process, a single-crystal structure yttrium oxide (Y2O3) layer is formed on the reconstruction surface of the GaAs layer. The atomic layer deposition process includes water or ozone gas as an oxygen source precursor and a cyclopentadienyl-type compound as an yttrium source precursor.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuanhsiung Chen, Minghwei Hong, Jueinai Kwo, Yen-Hsun Lin, Keng-Yung Lin
  • Patent number: 10158014
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a gate stack over the semiconductor substrate. The gate stack includes a high-k gate dielectric over the semiconductor substrate, and a magnetic compound over and in contact with the high-k gate dielectric. A source region and a drain region are on opposite sides of the gate stack. The gate stack, the source region, and the drain region are portions of a Metal-Oxide-Semiconductor (MOS) device.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: December 18, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Ming-Han Liao, Minghwei Hong
  • Patent number: 10032770
    Abstract: A multi-layered semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor layer, a first insulator layer, a second semiconductor layer, a second insulator layer, and a third semiconductor layer are formed over a substrate. A first transistor comprises the first semiconductor layer, the first insulator layer, and the second semiconductor layer, and a second transistor comprises the second semiconductor layer, the second insulator layer, and the third semiconductor layer.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 24, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Chi-Te Liang, Minghwei Hong, Fan-Hung Liu
  • Publication number: 20180151356
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, forming a high-? dielectric layer directly on the semiconductor layer as formed, and annealing the semiconductor layer, the high-dielectric layer, and the substrate. The semiconductor layer is a Group III-V compound semiconductor.
    Type: Application
    Filed: September 15, 2017
    Publication date: May 31, 2018
    Inventors: Chien-Hua FU, Keng-Yung LIN, Yen-Hsun LIN, Kuanhsiung CHEN, Juei-Nai KWO, Minghwei HONG
  • Publication number: 20170352539
    Abstract: A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.
    Type: Application
    Filed: April 14, 2017
    Publication date: December 7, 2017
    Inventors: Bo-Yu YANG, Minghwei HONG, Jueinai KWO, Yen-Hsun LIN, Keng-Yung LIN, Hsien-Wen WAN, Chao Kai CHENG, Kuan Chieh LU
  • Publication number: 20170213822
    Abstract: A multi-layered semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor layer, a first insulator layer, a second semiconductor layer, a second insulator layer, and a third semiconductor layer are formed over a substrate. A first transistor comprises the first semiconductor layer, the first insulator layer, and the second semiconductor layer, and a second transistor comprises the second semiconductor layer, the second insulator layer, and the third semiconductor layer.
    Type: Application
    Filed: April 10, 2017
    Publication date: July 27, 2017
    Inventors: Chi-Te Liang, Minghwei Hong, Fan-Hung Liu
  • Publication number: 20170207094
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a gate stack over the semiconductor substrate. The gate stack includes a high-k gate dielectric over the semiconductor substrate, and a magnetic compound over and in contact with the high-k gate dielectric. A source region and a drain region are on opposite sides of the gate stack. The gate stack, the source region, and the drain region are portions of a Metal-Oxide-Semiconductor (MOS) device.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Ming-Han Liao, Minghwei Hong
  • Patent number: 9620605
    Abstract: A multi-layered semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor layer, a first insulator layer, a second semiconductor layer, a second insulator layer, and a third semiconductor layer are formed over a substrate. A first transistor comprises the first semiconductor layer, the first insulator layer, and the second semiconductor layer, and a second transistor comprises the second semiconductor layer, the second insulator layer, and the third semiconductor layer.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: April 11, 2017
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Chi-Te Liang, Minghwei Hong, Fan-Hung Liu
  • Patent number: 9614079
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a gate stack over the semiconductor substrate. The gate stack includes a high-k gate dielectric over the semiconductor substrate, and a magnetic compound over and in contact with the high-k gate dielectric. A source region and a drain region are on opposite sides of the gate stack. The gate stack, the source region, and the drain region are portions of a Metal-Oxide-Semiconductor (MOS) device.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Han Liao, Minghwei Hong
  • Publication number: 20160336416
    Abstract: A multi-layered semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor layer, a first insulator layer, a second semiconductor layer, a second insulator layer, and a third semiconductor layer are formed over a substrate. A first transistor comprises the first semiconductor layer, the first insulator layer, and the second semiconductor layer, and a second transistor comprises the second semiconductor layer, the second insulator layer, and the third semiconductor layer.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: Chi-Te Liang, Minghwei Hong, Fan-Hung Liu
  • Publication number: 20150287834
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a gate stack over the semiconductor substrate. The gate stack includes a high-k gate dielectric over the semiconductor substrate, and a magnetic compound over and in contact with the high-k gate dielectric. A source region and a drain region are on opposite sides of the gate stack. The gate stack, the source region, and the drain region are portions of a Metal-Oxide-Semiconductor (MOS) device.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 8, 2015
    Applicants: National Taiwan University, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Han Liao, Minghwei Hong
  • Patent number: 6495407
    Abstract: A novel method of forming a GaAs-based MOS structure comprises ion implantation after oxide formation, and subsequent slow heating and cooling, carried out such that essentially no interfacial defects that are detectable by high resolution transmission electron microscopy are formed. If the MOS structure is a MOS-FET then metal contacts are provided in conventional fashion. A post-metallization anneal can result in FETs that are substantially free of drain current/voltage hysteresis. MOS-FETs made according to the novel method can be produced with high yield and can have significantly increased lifetime, as compared to some prior art GaAs-based MOS-FETs.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: December 17, 2002
    Assignee: Agere Systems Inc.
    Inventors: Minghwei Hong, Jenn-Ming Kuo, Jueinai Raynien Kwo, Joseph Petrus Mannaerts, Yu-Chi Wang
  • Patent number: 6469357
    Abstract: We have found that a single crystal, single domain oxide layer of thickness less than 5 nm can be grown on a (100) oriented GaAs-based semiconductor substrate. Similar epitaxial oxide can be grown on GaN and GaN-based semiconductors. The oxide typically is a rare earth oxide of the Mn2 0 3 structure (e.g., Gd2O3). The oxide/semiconductor interface can be of high quality, with low interface state density, and the oxide layer can have low leakage current and high breakdown voltage. The low thickness and high dielectric constant of the oxide layer result in a MOS structure of high capacitance per unit area. Such a structure advantageously forms a GaAs-based MOS-FET.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: October 22, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Minghwei Hong, Ahmet Refik Kortan, Jueinai Raynien Kwo, Joseph Petrus Mannaerts