Abstract: Disclosed is a diamine compound represented by Formula (1), in which R1, R2, R3, R4, R5, X1, X2, X3, X4, m, n, a, b, c, and d are as defined herein. Also disclosed are a method for manufacturing the diamine compound, a composition including the diamine compound having a (chain alkoxy-methylene) phenyl group or a (hydroxyl-methylene) phenyl group, and a polymer including the (chain alkoxy-methylene) phenyl group or the (hydroxyl-methylene) phenyl group.

Abstract: A membrane touch panel device includes a circuit board unit, a light-blocking frame plate, a plurality of light-blocking tabs, and an operation panel unit that are stacked along a front-rear direction. The circuit board unit includes a circuit board having a plurality of keypad circuits, and a plurality of LEDs being electrically connected to the circuit board. A light transmission rate of the circuit board ranges from 0% to 20%. The light-blocking frame plate is stacked on the circuit board, and defines a hollow section provided for the LEDs to protrude thereinto. The light-blocking tabs are connected to the light-blocking frame plate such that the light-blocking tabs respectively cover the LEDs. The operation panel unit is stacked on the light-blocking frame plate, and has a plurality of key segments being respectively aligned with the keypad circuits, and being adapted to permit light generated by the LEDs to pass therethrough.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: An engine includes an engine shaft configured to rotate and cause one or more pistons to reciprocate within a cylinder chamber along an axis, each piston having a first piston part and piston stem to move in unison with or separately from a second piston part to define piston strokes for different thermal functions of the engine. The engine further includes a piston lever having a first end coupled to a movable fulcrum point and a second end coupled at a copy point to the piston stem, an actuation mechanism configured to move the piston lever and thereby the copy point, and a guide apparatus configured to dictate movement of the copy point in a direction substantially parallel to the cylinder axis.

Abstract: A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

Abstract: An engine includes an engine shaft configured to rotate and cause one or more pistons to reciprocate within a cylinder chamber along an axis, each piston having a first piston part and piston stem to move in unison with or separately from a second piston part to define piston strokes for different thermal functions of the engine. The engine further includes a piston lever having a first end coupled to a movable fulcrum point and a second end coupled at a copy point to the piston stem, an actuation mechanism configured to move the piston lever and thereby the copy point, and a guide apparatus configured to dictate movement of the copy point in a direction substantially parallel to the cylinder axis.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: A polisher includes a wafer carrier, a polishing head, a movement mechanism, and a rotation mechanism. The wafer carrier has a supporting surface. The supporting surface is configured to carry a wafer thereon. The polishing head is present above the wafer carrier. The polishing head has a polishing surface. The polishing surface of the polishing head is smaller than the supporting surface of the wafer carrier. The movement mechanism is configured to move the polishing head relative to the wafer carrier. The rotation mechanism is configured to rotate the polishing head relative to the wafer carrier.

Abstract: A polisher includes a wafer carrier, a polishing head, a movement mechanism, and a rotation mechanism. The wafer carrier has a supporting surface. The supporting surface is configured to carry a wafer thereon. The polishing head is present above the wafer carrier. The polishing head has a polishing surface. The polishing surface of the polishing head is smaller than the supporting surface of the wafer carrier. The movement mechanism is configured to move the polishing head relative to the wafer carrier. The rotation mechanism is configured to rotate the polishing head relative to the wafer carrier.

Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.

Abstract: A computing device may be joined to a cluster by discovering the device, determining whether the device is eligible to join the cluster, configuring the device, and assigning the device a cluster role. A device may be assigned to act as a cluster master, backup master, active device, standby device, or another role. The cluster master may be configured to assign tasks, such as network flow processing to the cluster devices. The cluster master and backup master may maintain global, run-time synchronization data pertaining to each of the network flows, shared resources, cluster configuration, and the like. The devices within the cluster may monitor one another. Monitoring may include transmitting status messages comprising indicators of device health to the other devices in the cluster. In the event a device satisfies failover conditions, a failover operation to replace the device with another standby device, may be performed.

Abstract: A pesticide-free physically pest-isolating transparent polymeric film is formed of a plastic film that has a thickness of 0.03˜1.00 mm and is perforated to include a plurality of holes. The holes have a hole size of 1˜30 mm and a distribution density of 1,000˜200,000 holes/M2 on the plastic film. The pesticide-free physically pest-isolating transparent polymeric film is proven as a simple but very effective way of pest control. It helps plants fully grow without being attacked by pests in a pesticide-free condition. Further, the pesticide-free physically pest-isolating transparent polymeric film is repeatedly usable, and is therefore an easily operable and economical agricultural aid ideal for use.

Abstract: A pesticide-free physically pest-isolating transparent polymeric film is formed of a plastic film that has a thickness of 0.03˜1.00 mm and is perforated to include a plurality of holes. The holes have a hole size of 1˜30 mm and a distribution density of 1000˜200000 holes/M2 on the plastic film. The pesticide-free physically pest-isolating transparent polymeric film is proven as a simple but very effective way of pest control. It helps plants fully grow without being attacked by pests in a pesticide-free condition. Further, the pesticide-free physically pest-isolating transparent polymeric film is repeatedly usable, and is therefore an easily operable and economical agricultural aid ideal for use.

Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.