Patents by Inventor Ming-Jie Huang

Ming-Jie Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200100376
    Abstract: Embodiments disclosed herein provide an apparatus to enable smooth and safe assembly of functional modules to computer chassis. The apparatus includes a chassis and a pair of racks mounted to the chassis. Each rack has a plurality of gear teeth formed thereon. A module having a housing is slidably coupled to the chassis and disposed between the pair of racks. A pair of gear pinions are rotatably mounted to the housing and meshed to the gear teeth of one of the racks. A damping member is coupled between each gear pinion and the housing. A sliding movement of the housing relative to the chassis rotates the pair of gear pinions to roll over along the gear teeth. During the sliding movement of the housing, the damping member exerts a resistance force against the housing, to reduce the movement speed of the housing.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 26, 2020
    Inventors: CHANG-HSING LEE, CHIA-CHING HUANG, TA-WEI CHEN, SUNG-FENG CHEN, MING JIE CHAI
  • Publication number: 20190088499
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Application
    Filed: November 2, 2018
    Publication date: March 21, 2019
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Patent number: 10186511
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • Patent number: 10134604
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Publication number: 20180315618
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Application
    Filed: October 5, 2017
    Publication date: November 1, 2018
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Publication number: 20180204836
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • Patent number: 9917085
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • Publication number: 20170345820
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 30, 2017
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • Patent number: 9543210
    Abstract: A method includes forming a first mask over a substrate through a double patterning process, wherein the first mask comprises a horizontal portion and a plurality of vertical portions protruding over the horizontal portion, and wherein the vertical portions are spaced apart from each other, applying a first etching process to the first mask until a top surface of a portion of the substrate is exposed, applying a second etching process to the substrate to form intra-device openings and inter-device openings, wherein the inter-device openings are formed at the exposed portion of the substrate, filling the inter-device openings and the intra-device openings to form inter-device insulation regions and intra-device insulation regions and etching back the inter-device insulation regions and the intra-device insulation regions to form a plurality of fins protruding over top surfaces of the inter-device insulation regions and the intra-device insulation regions.
    Type: Grant
    Filed: September 5, 2015
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ping Chen, Hui-Min Lin, Ming-Jie Huang, Tung Ying Lee
  • Patent number: 9412666
    Abstract: A method of forming a semiconductor integrated circuit (IC) includes forming a first semiconductor layer over a substrate, the first semiconductor layer having an uneven upper surface, forming a stop layer over the first semiconductor layer, the first semiconductor layer disposed between the substrate and the stop layer, and treating the stop layer to change its etch selectivity relative to the first semiconductor layer.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Cheng Chen, Ming-Jie Huang, Yu Chao Lin
  • Publication number: 20160126142
    Abstract: A method of forming a semiconductor integrated circuit (IC) includes forming a first semiconductor layer over a substrate, the first semiconductor layer having an uneven upper surface, forming a stop layer over the first semiconductor layer, the first semiconductor layer disposed between the substrate and the stop layer, and treating the stop layer to change its etch selectivity relative to the first semiconductor layer.
    Type: Application
    Filed: November 11, 2015
    Publication date: May 5, 2016
    Inventors: Chao-Cheng Chen, Ming-Jie Huang, Yu Chao Lin
  • Publication number: 20150380315
    Abstract: A method includes forming a first mask over a substrate through a double patterning process, wherein the first mask comprises a horizontal portion and a plurality of vertical portions protruding over the horizontal portion, and wherein the vertical portions are spaced apart from each other, applying a first etching process to the first mask until a top surface of a portion of the substrate is exposed, applying a second etching process to the substrate to form intra-device openings and inter-device openings, wherein the inter-device openings are formed at the exposed portion of the substrate, filling the inter-device openings and the intra-device openings to form inter-device insulation regions and intra-device insulation regions and etching back the inter-device insulation regions and the intra-device insulation regions to form a plurality of fins protruding over top surfaces of the inter-device insulation regions and the intra-device insulation regions.
    Type: Application
    Filed: September 5, 2015
    Publication date: December 31, 2015
    Inventors: Chen-Ping Chen, Hui-Min Lin, Ming-Jie Huang, Tung Ying Lee
  • Patent number: 9214358
    Abstract: A method of forming a semiconductor integrated circuit (IC) that has substantially equal gate heights regardless of different pattern densities in different regions of the IC includes providing a substrate with a first pattern density in a first region of the IC and a second pattern density in a second region of the IC, forming a first polysilicon layer above the substrate, the first polysilicon layer having an uneven upper surface, forming a stop layer above the first polysilicon layer, treating the stop layer to change its etch selectivity relative to the first polysilicon layer, forming a second polysilicon layer above the stop layer, removing the second polysilicon layer, the stop layer, and a top portion of the first polysilicon layer, the remaining portion of the first polysilicon layer having a planar upper surface.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Ming-Jie Huang, Chao-Cheng Chen
  • Patent number: 9130058
    Abstract: A device includes a plurality of intra-device insulation regions having a first height; and a plurality of semiconductor fins horizontally spaced apart from each other by the plurality of intra-device insulation regions. A portion of the plurality of semiconductor fins is disposed above the plurality of intra-device insulation regions. The device further includes a first inter-device insulation region and a second inter-device insulation region with the plurality of semiconductor fins disposed therebetween. The first and the second inter-device insulation regions have a second height greater than the first height.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ping Chen, Hui-Min Lin, Ming-Jie Huang, Tung Ying Lee
  • Patent number: 8900957
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
  • Patent number: 8900956
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
  • Patent number: 8877614
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Ko, Jyh-Huei Chen, Ming-Jie Huang
  • Patent number: 8835242
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Ko, Jyh-Huei Chen, Ming-Jie Huang
  • Publication number: 20140162432
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 12, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Ko, Jyh-Huei Chen, Ming-Jie Huang
  • Patent number: 8692353
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Ko, Jyh-Huei Chen, Ming-Jie Huang