Patents by Inventor Ming-Ju E. Lee
Ming-Ju E. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9798353Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.Type: GrantFiled: June 18, 2013Date of Patent: October 24, 2017Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Aaron J. Nygren, Ming-Ju E. Lee, Shadi M. Barakat, Xiaoling Xu, Toan D. Pham, W. Fritz Kruger, Michael J. Litt
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Patent number: 8892963Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.Type: GrantFiled: November 9, 2006Date of Patent: November 18, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 8775747Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.Type: GrantFiled: March 19, 2013Date of Patent: July 8, 2014Assignee: ATI Technologies ULCInventors: Joseph D. Macri, Stephen Morein, Ming-Ju E. Lee, Lin Chen
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Patent number: 8661300Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.Type: GrantFiled: June 27, 2011Date of Patent: February 25, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Publication number: 20130290767Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.Type: ApplicationFiled: June 18, 2013Publication date: October 31, 2013Inventors: Aaron J. NYGREN, Ming-Ju E. Lee, Shadi M. Barakat, Xiaoling Xu, Toan D. Pham, W. Fritz Kruger, Michael J. Litt
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Patent number: 8564347Abstract: Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating phase shifted clock signals, a phase detector receiving the system clock signal and phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.Type: GrantFiled: September 7, 2012Date of Patent: October 22, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Min Xu, Ming-Ju E. Lee
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Patent number: 8429356Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.Type: GrantFiled: February 22, 2006Date of Patent: April 23, 2013Assignee: ATI Technologies ULCInventors: Joseph D. Macri, Stephen Morein, Ming-Ju E. Lee, Lin Chen
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Publication number: 20130057328Abstract: Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating phase shifted clock signals, a phase detector receiving the system clock signal and phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.Type: ApplicationFiled: September 7, 2012Publication date: March 7, 2013Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Min XU, Ming-Ju E. LEE
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Patent number: 8301930Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.Type: GrantFiled: January 21, 2009Date of Patent: October 30, 2012Assignee: ATI Technologies, Inc.Inventors: Stephen Morein, Joseph Macri, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 8289056Abstract: Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals.Type: GrantFiled: December 3, 2008Date of Patent: October 16, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Min Xu, Ming-Ju E. Lee
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Patent number: 7996731Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.Type: GrantFiled: November 1, 2006Date of Patent: August 9, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 7934109Abstract: Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.Type: GrantFiled: April 3, 2007Date of Patent: April 26, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Steven Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 7869525Abstract: A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.Type: GrantFiled: February 17, 2006Date of Patent: January 11, 2011Assignee: ATI Technologies, Inc.Inventors: Joseph D. Macri, Stephen Morein, Ming-Ju E. Lee, Lin Chen
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Patent number: 7752476Abstract: Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.Type: GrantFiled: May 17, 2007Date of Patent: July 6, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Steven Morein, Ming-Ju E. Lee, Lin Chen
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Publication number: 20100134161Abstract: Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals.Type: ApplicationFiled: December 3, 2008Publication date: June 3, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Min Xu, Ming-Ju E. Lee
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Patent number: 7663398Abstract: A circuit including control logic; and configurable impedance logic, operatively coupled to the control logic, comprising a configurable transistor structure operative to selectively change from a high impedance mode where the configurable transistor structure is configurable as a plurality of series connected diodes having their cathodes coupled together, and a low impedance mode where the configurable transistor structure is configurable to include a plurality of cascoded transistors. The circuit may further include at least one control signal line from the control logic to the configurable impedance logic, where the control signal line is operative to provide a control signal for configuring the configurable impedance logic.Type: GrantFiled: November 18, 2008Date of Patent: February 16, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Jaeseo Lee, Gin S. Yee, Ming-Ju E. Lee
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Publication number: 20090125747Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.Type: ApplicationFiled: January 21, 2009Publication date: May 14, 2009Applicant: ATI TECHNOLOGIES, INC.Inventors: Stephen Morein, Joseph Macri, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 7509515Abstract: A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.Type: GrantFiled: September 19, 2005Date of Patent: March 24, 2009Assignee: ATI Technologies, Inc.Inventors: Joseph Macri, Steven Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 7487378Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.Type: GrantFiled: September 19, 2005Date of Patent: February 3, 2009Assignee: ATI Technologies, Inc.Inventors: Stephen Morein, Joseph Macri, Claude Gauthier, Ming-Ju E. Lee, Lin Chen