Abstract: A semiconductor wafer including a substrate, a copper dual damascene structure positioned on the substrate, a dielectric layer covering the copper dual damascene structure, and a via hole positioned in the dielectric layer, the hole continuing to a surface of the copper layer. First, a tantalum nitride (TaN) layer is formed on a bottom surface within the via hole and on walls within the via hole. A titanium nitride (TiN) layer is then formed on the tantalum nitride layer. By performing a chemical vapor deposition (CVD) process, a tungsten layer is formed to cover a surface of the titanium nitride layer as well as to fill the via hole. Finally, a chemical mechanical polishing (CMP) process is performed to make a top of the tungsten layer in the via hole aligned with the surface of the dielectric layer so as to form a tungsten plug.