Abstract: A foreign object detection method for detecting whether a foreign object exists on a function pin of a power supplier side or a power receiver side, wherein the power supplier side and the power receiver side are coupled to each other in a detachable fashion. The foreign object detection method includes: discharging a capacitor via the function pin, wherein the capacitor is electrically connected to the function pin; providing a sensing current flowing through the function pin, to charge the capacitor; sensing a voltage variation of the function pin during a predetermined period; and comparing the voltage variation with a predetermined variation, so as to determine whether a foreign object exists on the function pin.

Abstract: A calibration method is configured for calibrating an operation circuit which has a variant offset. The operation circuit includes at least one comparator circuit having a first variant offset. The calibration method provides an adjustable offset to calibrate the variant offset. The method includes: resetting an adjustment parameter to an initial value and configuring the operation circuit to a calibration mode; conducting an initial calibration procedure according to a comparison result of the comparator circuit, to decide an operation calibration code having plural bits; configuring the operation circuit to an operation mode; conducting a predetermined operation procedure according to the operation calibration code, wherein the operation calibration code corresponds to the adjustable offset; conducting a less bit number calibration procedure according to the adjustment parameter and a test calibration code to update the adjustment parameter or the operation calibration code; and repeating the above.

Abstract: An electronic device for controlling an LRA (Linear Resonant Actuator) includes a signal generator, a driver, a delay unit, a sensor, and a DSP (Digital Signal Processor). The signal generator generates a digital signal. The driver drives the LRA according to the digital signal. The delay unit delays the digital signal for a predetermined time, so as to generate an estimated voltage signal. The sensor detects the current flowing through the LRA, so as to generate a sensing current signal. The DSP controls the resonant frequency or the gain value of the signal generator according to the estimated voltage signal and the sensing current signal.

Abstract: A class-D amplifying system includes: a class-D amplifier circuit configured to convert an input signal to a switch control signal in pulse width modulation fashion, wherein the switch control signal controls switches to operate a first inductor and a second inductor, thus converting an input power to a positive output signal and a negative output signal which are complementary to each other, to thereby drive a load; and a power converter circuit, which generates a direct current (DC) power supply according to at least one of the positive output signal and the negative output signal, wherein the DC power supply supplies at least a portion of power to the class-D amplifier circuit.

Abstract: A foreign object detection method for detecting whether a foreign object exists on a function pin of a power supplier side or a power receiver side, wherein the power supplier side and the power receiver side are coupled to each other in a detachable fashion. The foreign object detection method includes: discharging a capacitor via the function pin, wherein the capacitor is electrically connected to the function pin; providing a sensing current flowing through the function pin, to charge the capacitor; sensing a voltage variation of the function pin during a predetermined period; and comparing the voltage variation with a predetermined variation, so as to determine whether a foreign object exists on the function pin.

Abstract: A BD type pulse width modulation (PWM) circuit is configured to convert a pair of complementary input signals to a pair of output PWM signals. The BD PWM circuit modulates a basic modulation signal according to the pair of input signals, to generate a basic PWM signal. The common mode levels of the pair of input signals and the basic modulation signal are the same. The BD PWM circuit modulates an offset modulation signal according to the pair of input signals to generate an offset PWM signal. The offset modulation signal and the basic modulation signal have a non-zero offset in between. The BD PWM circuit selects the offset PWM signal or a heavy load PWM signal as the pair of output PWM signals. The heavy load PWM signal is correlated with the basic PWM signal.

Abstract: A low distortion triangular wave generator circuit generates a triangular wave signal by performing integration on an integration capacitor via a charging current and a discharging current during a charging period and a discharging period within a switching period of an external clock signal. A time length of the charging period is identical to a time length of the discharging period. A common mode related signal related to a common mode characteristic of the triangular wave signal is generated. An adjusting signal is generated according to a difference between the common mode related signal and a predetermined DC (direct current) level. The adjusting signal adjusts at least one of the charging current and the discharging current via feedback mechanism such that the triangular wave signal is a symmetrical triangular wave, and an average voltage of the triangular wave signal is equal to a target DC level.

Abstract: A low distortion triangular wave generator circuit generates a triangular wave signal by performing integration on an integration capacitor via a charging current and a discharging current during a charging period and a discharging period within a switching period of an external clock signal. A time length of the charging period is identical to a time length of the discharging period. A common mode related signal related to a common mode characteristic of the triangular wave signal is generated. An adjusting signal is generated according to a difference between the common mode related signal and a predetermined DC (direct current) level. The adjusting signal adjusts at least one of the charging current and the discharging current via feedback mechanism such that the triangular wave signal is a symmetrical triangular wave, and an average voltage of the triangular wave signal is equal to a target DC level.

Abstract: A DAC circuit includes: a PWM encoding circuit for converting a digital signal to first and second PWM signals, whereby a combination of the first and second PWM signals becomes a PWM encoded signal of at least 3 levels including a positive, a zero and a negative level, wherein the digital signal represents a number in a numerical range; and a demodulation circuit for generating the analog signal according to the first and second PWM signals. The first and second PWM signals have a minimum duty larger than 0 when the digital signal represents a middle number in the numerical range. The zero level of the combination of the first and second PWM signals has a duty which decreases as a difference between the number represented by the digital signal and the middle number increases.

Abstract: A voltage adjusting circuit includes a reference voltage generating circuit, a subtractor circuit, a threshold generating circuit and a comparator circuit. The voltage adjusting circuit may provide power supply signals to an amplifier circuit so that the amplifier circuit may provide an output signal to a load according to an input signal. The subtractor circuit generates a difference signal according to the output signal and the power supply signal. The comparator circuit compares the difference signal and a threshold signal generated by the threshold generating circuit for configuring the reference voltage generating circuit to adjust the signal value of the power supply signal.

Abstract: A voltage adjusting circuit includes a reference voltage generating circuit, a subtractor circuit, a threshold generating circuit and a comparator circuit. The voltage adjusting circuit may provide power supply signals to an amplifier circuit so that the amplifier circuit may provide an output signal to a load according to an input signal. The subtractor circuit generates a difference signal according to the output signal and the power supply signal. The comparator circuit compares the difference signal and a threshold signal generated by the threshold generating circuit for configuring the reference voltage generating circuit to adjust the signal value of the power supply signal.

Abstract: The present invention discloses a short-circuit detection circuit and a short-circuit detection method. The short-circuit detection circuit detects whether an output node is short-circuited to a first predetermined level. A first switch circuit which is controlled by a control signal is coupled between the output node and a second predetermined level. The short-circuit detection circuit includes: a determination circuit, which is coupled between the output node and the second predetermined level, wherein when the determination circuit is enabled, it generates a determination signal according to whether the output node is short-circuited to the first predetermined level; and a second switch circuit, which generates a short-circuit detection signal according to the determination signal.

Abstract: A dual mode charge pump is operable in a first mode or a second mode for providing positive and negative output voltages that can be stabilized by adjusting the charging time of two terminals of a flying capacitor or by adjusting the charging/discharging time of the positive and negative voltage output terminals. The dual mode charge pump can apply to a much wider input supply voltage range with less numbers of power switches, thus requiring less die area and lower costs. Moreover, the dual mode charge pump can precisely define a common mode voltage, thus making the common voltage drift smaller and less load dependent, especially when the output supply voltages are under different load conditions.

Abstract: The present invention discloses a short-circuit detection circuit and a short-circuit detection method. The short-circuit detection circuit detects whether an output node is short-circuited to a first predetermined level. A first switch circuit which is controlled by a control signal is coupled between the output node and a second predetermined level. The short-circuit detection circuit includes: a determination circuit, which is coupled between the output node and the second predetermined level, wherein when the determination circuit is enabled, it generates a determination signal according to whether the output node is short-circuited to the first predetermined level; and a second switch circuit, which generates a short-circuit detection signal according to the determination signal.

Abstract: A device and method is provided to selectively modify the transmission performance of a frame data. Through a parallel transmission interface, the frame data is transmitted under a corresponding interface protocol and transmitted toward an image display. The method first detects a data size of the frame data and then provides a transmission control signal based on the detection of the data size. Next, selectively divide the frame data by a factor M based on the transmission control signal. Furthermore, transmit the divided frame data at a raised clock rate based on the factor M. Afterwards, temporarily store the divided frame data about to be transmitted toward the image display until the whole frame data is transmitted.

Abstract: A dual mode charge pump is operable in a first mode or a second mode for providing positive and negative output voltages that can be stabilized by adjusting the charging time of two terminals of a flying capacitor or by adjusting the charging/discharging time of the positive and negative voltage output terminals. The dual mode charge pump can apply to a much wider input supply voltage range with less numbers of power switches, thus requiring less die area and lower costs. Moreover, the dual mode charge pump can precisely define a common mode voltage, thus making the common voltage drift smaller and less load dependent, especially when the output supply voltages are under different load conditions.

Abstract: A mobile communication terminal system includes a serial interface port, a multimedia output/input module, a multimedia processor, a frequency-signal output/input module, and a baseband processor. The serial interface port is coupled to a computer system via a serial interface. The multimedia output/input module provides a first input signal. The multimedia processor processes the first input signal to generate a first serial interface signal. The frequency-signal output/input module provides a second input signal. The baseband processor processes the second input signal to generate a second serial interface signal to the multimedia processor.

Abstract: The present invention discloses a multi-channel multi-media data processing method, comprising the steps of: providing a demodulator circuit and a multi-media processing circuit, the multi-media processing circuit including a DRAM; receiving multi-channel analog signals, and performing analog-to-digital conversion and demodulation on the signals by the demodulator circuit; storing the converted and demodulated multi-channel signals in the DRAM; and reading the signals of at least one channel from the DRAM.

Abstract: A mobile communication terminal system includes a serial interface port, a multimedia output/input module, a multimedia processor, a frequency-signal output/input module, and a baseband processor. The serial interface port is coupled to a computer system via a serial interface. The multimedia output/input module provides a first input signal. The multimedia processor processes the first input signal to generate a first serial interface signal. The frequency-signal output/input module provides a second input signal. The baseband processor processes the second input signal to generate a second serial interface signal to the multimedia processor.

Abstract: A device and method is provided to selectively modify the transmission performance of a frame data. Through a parallel transmission interface, the frame data is transmitted under a corresponding interface protocol and transmitted toward an image display. The method first detects a data size of the frame data and then provides a transmission control signal based on the detection of the data size. Next, selectively divide the frame data by a factor M based on the transmission control signal. Furthermore, transmit the divided frame data at a raised clock rate based on the factor M. Afterwards, temporarily store the divided frame data about to be transmitted toward the image display until the whole frame data is transmitted.