Abstract: A method for manufacturing a semiconductor device includes: forming a plurality of sacrificial stack portions on a semiconductor substrate, the sacrificial stack portions being spaced apart from each other; forming a metal material layer to cover the sacrificial stack portions, the metal material layer including a first metal and a second metal different from the first metal, the first metal having a reduction potential lower than that of the second metal; and annealing the metal material layer to form a self-forming barrier layer conformally covering the sacrificial stack portions, the self-forming barrier layer including a metal oxide, a metal silicide, or a combination thereof formed from the first metal by annealing.

Abstract: An interconnect structure, along with methods of forming such, are described. The structure includes a dielectric layer, a conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer, wherein the conductive layer includes a first portion and a second portion adjacent the first portion. The structure also includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a dielectric material disposed between and in contact with the first and second barrier layers, wherein a bottom surface of the second barrier layer and a bottom surface of the dielectric material are substantially co-planar.

Abstract: The present invention provides a wafer container and a gas diffusion device applied in the wafer container. The wafer container includes a shell, and all components included and applied on the shell are made of thermal resistance materials. The gas diffusion device and the wafer container, when assembled together, utilize a coupling structure and a collar as a protection mechanism for the gas diffusion device. The gas diffusion device has a buffering chamber that provides a buffering tolerance and a communicating space for the gas before the gas enters an interior space of the wafer container.

Abstract: The present disclosure provides a semiconductor device that includes a substrate, a first dielectric layer over the substrate, and an interconnect layer over the first dielectric layer. The interconnect layer includes a plurality of metal lines and a second dielectric layer filling space between the plurality of metal lines. The plurality of metal lines includes a first metal line having a first bulk metal layer of a noble metal and a second metal line having a second bulk metal layer of a non-noble metal.

Abstract: Methods and pharmaceutical compositions for the treatment of BAP1 deficient cancer are based on investigation of the role of BET (Bromodomain and Extra-Terminal motif proteins) in BAP1 deficient cancer and screened isogenic cells (BAP1 WT vs KO). BET inhibitors show more anti-proliferative activity against cells KO for BAP1. Using isogenic cell lines and uveal melanoma PDX derived cell lines with different status of expression for BAP1 showed a highest dose response to a BET inhibitors (OTX015 and BI894999) in BAP1 KO isogenic cells compared to WT cells and an enhanced dose response to OTX015 in a BAP1 mutated uveal melanoma (UM) derived cells compared to UM cells expressing BAP1. BET inhibitors have a role in BAP1 deficient cancer, and BET inhibitors are useful in the treatment of BAP1 deficient cancer, particularly BAP1 deficient Uveal Melanoma, clear cell Renal Carcinoma, cholangiocarcinoma and mesothelioma.