Abstract: An electronic package module including a circuit substrate, an electronic component disposed on the circuit substrate and a molding compound is provided. The molding compound encapsulates the circuit substrate and the electronic component. The circuit substrate includes a first circuit layer and a first insulation layer covering on the first circuit layer. The first insulation layer has a boundary surface where a second circuit layer is disposed. A second insulation layer covers a part of the second circuit layer while the insulation layer bares a region surrounding the perimeter of the boundary surface. The molding compound directly contacts the region and the second insulation layer.

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.

Abstract: A display substrate, comprising: a base, a circuit structure layer, a light-transmitting structure layer, and a light-emitting structure layer. The circuit structure layer is located in a second region and comprises a plurality of first pixel circuits. The light-transmitting structure layer is located in a first region and comprises a shielding layer and at least one connecting layer. Orthographic projections of the shielding layer and of at least one connecting layer at least partially overlap on the base. The at least one connecting layer comprises a plurality of first connecting lines, at least one first connecting line extending from the first region to the second region. The light-emitting structure layer comprises a plurality of first light-emitting elements located in the first region. At least one first light-emitting element is electrically connected to at least one first pixel circuit by means of at least one first connecting line.

Abstract: A bidirectional hybrid power conversion system includes a symmetric hybrid unit, a transient state detection unit, a conversion control unit, and a feedback unit. The symmetric hybrid unit converts an input voltage into an output voltage with different conversion ratios. The feedback unit generates a feedback signal according to the output voltage and a reference voltage. The conversion control unit is connected with the symmetric hybrid unit and the feedback unit controls the symmetric hybrid unit to adjust the conversion ratio for regulating the output voltage according to the feedback signal. The transient state detection unit is connected with the feedback unit and the conversion control unit outputs a detection signal to the conversion unit according to the feedback signal. According to the detection signal, the conversion control unit controls the symmetric hybrid unit adjusts the conversion ratio, and converts the input voltage into the output voltage stably.

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

Abstract: The present invention provides a PTX3 monoclonal antibody or antibody Fab fragment thereof and use thereof. The aforementioned monoclonal antibody or antibody Fab fragment thereof specifically inhibit or slow down the binding of PTX3 to the PTX3 receptor, and may be used for a kit and method for detecting PTX3, and a pharmaceutical composition which inhibits or slows down diseases or symptoms associated with PTX3 and PTX3 receptor binding, and a use thereof.

Abstract: A method includes forming a first fin structure and a second fin structure protruding from a substrate, forming a dielectric fin between the first fin structure and the second fin structure, recessing the dielectric fin to form a trench between the first fin structure and the second fin structure, and depositing a first dielectric layer on sidewall surfaces of the trench and on a top surface of the recessed dielectric fin. After the depositing the first dielectric layer, a second dielectric layer is deposited in the trench. The method further includes depositing a third dielectric layer to cap the second dielectric layer in the trench, and forming a gate structure on the first fin structure, the second fin structure, and the third dielectric layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.

Abstract: A driving device includes a first current source, a second current source, a first common-mode current elimination (CMCE) circuit, a second common-mode current elimination (CMCE) circuit, a current-to-voltage converter, and a first comparator. The current sources provide constant currents. The current-to-voltage converter includes a first current mirror and a second current mirror. The control terminal of the first current mirror is coupled to the second CMCE circuit. The control terminal of the second current mirror is coupled to the first CMCE circuit. The first current mirror and the second current mirror receive the constant currents, common-mode currents, and differential currents, thereby controlling the first CMCE circuit and the second CMCE circuit to generate a voltage difference that excludes a common-mode voltage corresponding to the common-mode currents. The first comparator receives the voltage difference to drive a field-effect transistor.

Abstract: A semiconductor device includes a fin disposed on a substrate, a first dielectric layer disposed over the fin, a first contact extending through the first dielectric layer to a first depth and electrically coupled to the fin, and a second contact extending through the first dielectric layer to a second depth different than the first depth. The first contact has a first bottom portion having a first cross-sectional shape profile. The second contact being electrically isolated from the fin and having a second bottom portion having a second cross-sectional shape profile different than the first cross-sectional shape profile. The semiconductor device also includes a first protective layer disposed along the first contact without being disposed on at least a portion of the first bottom portion of the first contact, and a second protective layer disposed along the second contact including along the second bottom portion of the second contact.

Abstract: A semiconductor structure includes a first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die; and a molding material encapsulating the first die, the first conductive vias, the second conductive vias and the third conductive vias. A first width of each of the plurality of first conductive vias, a second width of each of the plurality of second conductive vias and a third width of the plurality of third conductive vias are different from each other.

Abstract: A method for identifying objects by shape in close proximity to other objects of different shapes obtains point cloud information of multiple objects. The objects are arranged in at least two trays and the trays are stacked. A depth image of the objects is obtained according to the point cloud information, and the depth image of the objects is separated and layered to obtain a layer information of all the objects. An object identification system also disclosed. Three-dimensional machine vision is utilized in identifying the objects, improving the accuracy of object identification, and enabling the mechanical arm to accurately grasp the required object.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.

Abstract: A semiconductor device includes a pair of fin structures on a semiconductor substrate, each including a vertically stacked plurality of channel layers, a dielectric fin extending in parallel to and between the fin structures, and a gate structure on and extending perpendicularly to the fin structures, the gate structure engaging with the plurality of channel layers. The dielectric fin includes a fin bottom and a fin top over the fin bottom. The fin bottom has a top surface extending above a bottom surface of a topmost channel layer. The fin top includes a core and a shell, the core having a first dielectric material, the shell surrounding the core and having a second dielectric material different from the first dielectric material.

Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.

Abstract: A method for preparing a carbide protective layer comprises: (A) mixing a carbide powder, an organic binder, an organic solvent and a sintering aid to form a slurry; (B) spraying the slurry on a surface of a graphite component to form a composite component; (C) subjecting the composite component to a cold isostatic pressing densification process; (D) subjecting the composite component to a constant temperature heat treatment; (E) repeating steps (B)-(D) until a coating is formed on a surface of the composite component; (F) subjecting the coating to a segmented sintering process; (G) obtaining a carbide protective layer used for the surface of the composite component. Accordingly, while the carbide protective layer can be completed by using the wet cold isostatic pressing densification process and the cyclic multiple superimposition method, so that it can improve the corrosion resistance in the silicon carbide crystal growth process environment.

Abstract: A display panel includes pixel circuits, and the pixel circuit includes: a driving sub-circuit, a fourth sub-circuit and a first reset sub-circuit. The driving sub-circuit includes a driving transistor and a storage capacitor. The driving transistor includes a gate and an active pattern including a source portion and a drain portion. The storage capacitor includes a first storage electrode sharing a same electrode with the gate and a second storage electrode used to be connected to a first voltage signal line. The fourth sub-circuit is configured such that the drain portion and the gate are connected when being turned on. The first reset sub-circuit includes a first active pattern, which is arranged in a same layer as the active pattern and includes a first source portion being used to be connected to a first initialization signal line and a first drain portion being connected to the drain portion.

Abstract: Disclosed herein is a microfluidic mixer comprising first and second input chambers, first and second flow paths, and an output chamber. According to embodiments of the present disclosure, the first input chamber and the output chamber respectively have their bottom surfaces leveled with that of the first and/or second flow paths, while the second input chamber has its bottom surface protruded below that of the first flow path. Also disclosed herein is a microfluidic system comprising the present microfluidic mixer, and a pump for introducing a first and a second fluid reactants respectively into the first and a second input chambers.

Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.