Patents by Inventor Ming-Kun Chen
Ming-Kun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240135990Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.Type: ApplicationFiled: December 28, 2023Publication date: April 25, 2024Applicant: Winbond Electronics Corp.Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
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Patent number: 9274167Abstract: A chip-to-chip signal transmission system is provided, which includes a first chip, a second chip, and a dielectric layer. A signal transmission is performed between a transmitter of the first chip and a receiver of the second chip through a transmission-metal-pad unit and a receiving-metal-pad unit. The transmitter transmits a transmission-testing-coupling signal through the transmission-metal-pad unit according to a driving-testing signal when the transmitter receives the driving-testing signal. A first testing unit receives the transmission-testing-coupling signal and outputs a transmission-testing signal according to the transmission-testing-coupling signal. A second testing unit transmits a receiving-testing-coupling signal through the receiving-metal-pad unit according to the driving-testing signal when the second testing unit receives the driving-testing signal.Type: GrantFiled: May 29, 2013Date of Patent: March 1, 2016Assignee: I-SHOU UNIVERSITYInventors: Yu-Jung Huang, Ming-Kun Chen, Kai-Jen Liu
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Publication number: 20150010092Abstract: A signal transmission system and a signal transmission circuit are provided. The system includes a first chip and a second chip. A rising pulse signal (RPS) and a falling pulse signal (FPS) are generated by a transmission module on the first chip in response to a waveform of an input signal.Type: ApplicationFiled: October 15, 2013Publication date: January 8, 2015Applicant: I-SHOU UNIVERSITYInventors: Chun-Wei Huang, Yu-Jung Huang, Ming-Kun Chen
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Patent number: 8913687Abstract: A signal transmission system and a signal transmission circuit are provided. The system includes a first chip and a second chip. A rising pulse signal (RPS) and a falling pulse signal (FPS) are generated by a transmission module on the first chip in response to a waveform of an input signal. The RPS corresponds to rising edges of the input signal, the FPS corresponds to falling edges of the input signal, and the RPS and the FPS are transmitted by a first transmission unit and a second transmission unit both located on a surface of the first chip.Type: GrantFiled: October 15, 2013Date of Patent: December 16, 2014Assignee: I-Shou UniversityInventors: Chun-Wei Huang, Yu-Jung Huang, Ming-Kun Chen
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Publication number: 20140210496Abstract: A chip-to-chip signal transmission system is provided, which includes a first chip, a second chip, and a dielectric layer. A signal transmission is performed between a transmitter of the first chip and a receiver of the second chip through a transmission-metal-pad unit and a receiving-metal-pad unit. The transmitter transmits a transmission-testing-coupling signal through the transmission-metal-pad unit according to a driving-testing signal when the transmitter receives the driving-testing signal. A first testing unit receives the transmission-testing-coupling signal and outputs a transmission-testing signal according to the transmission-testing-coupling signal. A second testing unit transmits a receiving-testing-coupling signal through the receiving-metal-pad unit according to the driving-testing signal when the second testing unit receives the driving-testing signal.Type: ApplicationFiled: May 29, 2013Publication date: July 31, 2014Applicant: I-SHOU UNIVERSITYInventors: Yu-Jung Huang, Ming-Kun Chen, Kai-Jen Liu
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Patent number: 8592982Abstract: A semiconductor package includes a semiconductor structure. The semiconductor structure includes a plurality of dielectric layers and a plurality of conductive interconnects embedded in the semiconductor structure. The semiconductor structure also includes a plurality of proximity communication signal input terminals. At least one of the plurality of proximity communication signal input terminals includes a first electrode and a second electrode. The first electrode and the second electrode are spaced apart so as to be configured to provide proximity communication through capacitive coupling. The first electrode is exposed proximate to a surface of the semiconductor structure.Type: GrantFiled: October 4, 2011Date of Patent: November 26, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Tai-Ping Wang, Ming-Hsiang Cheng
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Patent number: 8421491Abstract: Provided is an active non-contact probe card including a carrier, a support base, a piezoelectric material layer, an active sensor array chip and a control circuit. The support base is disposed on the carrier. The piezoelectric material layer is connected with the support base. The position of the active sensor array chip with respect to the carrier is determined according to the thicknesses of the support base and the thicknesses of the piezoelectric material layer. A control circuit provides a control voltage to the piezoelectric material layer to control the thickness of the piezoelectric material layer, so as to adjust the position of the active sensor array chip with respect to the carrier.Type: GrantFiled: March 12, 2010Date of Patent: April 16, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ming-Kun Chen, Yi-Lung Lin
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Patent number: 8368216Abstract: The present invention relates to a semiconductor package having at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface upon which the first metal bumps are disposed and a plurality of first signal coupling pads disposed adjacent to the first active surface. The second layer chip is electrically connected to the first layer chip, and includes a second active surface that faces the first active surface and a plurality of second signal coupling pads. The second signal coupling pads are capacitively coupled to the first signal coupling pads so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps, and the second layer chip, and the first metal bumps are partially exposed.Type: GrantFiled: August 31, 2010Date of Patent: February 5, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Patent number: 8253431Abstract: The present invention relates to an apparatus and a method for testing non-contact pads of a semiconductor device to be tested. The apparatus includes an insulating body, at least one testing module and a plurality of probes. The insulating body includes an accommodating cavity, a lower opening and at least one side opening. The side opening communicates with the accommodating cavity and the lower opening. The testing module is disposed in the side opening, and each testing module includes a circuit board and an active chip. The active chip is disposed on and electrically connected to the circuit board. The active chip has a plurality of testing pads exposed to the accommodating cavity. The probes are disposed in the lower opening.Type: GrantFiled: May 20, 2010Date of Patent: August 28, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, I. L. Lin, Ken Juang, Ming-Hsiang Cheng
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Publication number: 20120153489Abstract: A semiconductor package includes a semiconductor structure. The semiconductor structure includes a plurality of dielectric layers and a plurality of conductive interconnects embedded in the semiconductor structure. The semiconductor structure also includes a plurality of proximity communication signal input terminals. At least one of the plurality of proximity communication signal input terminals includes a first electrode and a second electrode. The first electrode and the second electrode are spaced apart so as to be configured to provide proximity communication through capacitive coupling. The first electrode is exposed proximate to a surface of the semiconductor structure.Type: ApplicationFiled: October 4, 2011Publication date: June 21, 2012Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: YI-SHAO LAI, TSUNG-YUEH TSAI, MING-KUN CHEN, TAI-PING WANG, MING-HSIANG CHENG
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Publication number: 20120091575Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, at least one first chip, a dielectric layer and at least one second chip. The first chip is attached and electrically connected to the substrate. The first chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The dielectric layer is disposed on the first active surface. The second chip is attached and electrically connected to the substrate by metal bumps. The second chip includes a second active surface and a plurality of second signal coupling pads. The second active surface contacts the dielectric layer. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Publication number: 20120049360Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The first metal bumps are disposed on the first active surface of the first layer chip. The second layer chip is electrically connected to the first layer chip, and includes a second active surface and a plurality of second signal coupling pads. The second active surface faces the first active surface of the first layer chip. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first layer chip, so as to provide proximity communication between the first layer chip and the second layer chip.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Publication number: 20110309516Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Publication number: 20110298139Abstract: The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and a second chip. The substrate has a first surface, a second surface and at least one through hole. The first chip is disposed adjacent to the first surface of the substrate. The first chip includes a first active surface and a plurality of first signal pads. Part of the first active surface is exposed to the through hole. The position of the first signal pads corresponds to the through hole. The second chip is disposed adjacent to the second surface. The second chip includes a second active surface and a plurality of second signal pads. Part of the second active surface is exposed to the through hole. The position of the second signal pads corresponds to the through hole, and the second signal pads are capacitively coupled to the first signal pads of the first chip, so as to provide proximity communication between the first chip and the second chip.Type: ApplicationFiled: June 4, 2010Publication date: December 8, 2011Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Patent number: 8072064Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance.Type: GrantFiled: June 21, 2010Date of Patent: December 6, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Publication number: 20110291690Abstract: The present invention relates to an apparatus and a method for testing non-contact pads of a semiconductor device to be tested. The apparatus includes an insulating body, at least one testing module and a plurality of probes. The insulating body includes an accommodating cavity, a lower opening and at least one side opening. The side opening communicates with the accommodating cavity and the lower opening. The testing module is disposed in the side opening, and each testing module includes a circuit board and an active chip. The active chip is disposed on to and electrically connected to the circuit board. The active chip has a plurality of testing pads exposed to the accommodating cavity. The probes are disposed in the lower opening.Type: ApplicationFiled: May 20, 2010Publication date: December 1, 2011Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, I.L. Lin, Ken Juang, Ming-Hsiang Cheng
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Publication number: 20110278739Abstract: The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and an interposer. The first chip is mechanically and electrically connected to the substrate. Some signal pads of the interposer are capacitively coupled to some signal pads of the first chip, so as to provide proximity communication between the first chip and the interposer. Whereby, the capacitively coupled signal pads can be made in fine pitch, and therefore the size of the semiconductor package is reduced and the density of the signal pads is increased.Type: ApplicationFiled: May 11, 2010Publication date: November 17, 2011Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Publication number: 20110156739Abstract: A test kit for testing a chip subassembly and a testing method by using the same is provided. The chip subassembly includes at least two stacked chips each having a number of electric contacts is provided. The test kit includes a test socket and a test plate. The test socket is configured to electrically engage the electric contacts on a first side of the chip subassembly. The test plate has at least a number of first probes configured for electrically engaging the electric contacts on a second side of the chip subassembly. At least one of the test socket and the test plate has a number of second probes for electrically connecting the test socket and the test plate.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Inventors: Hsiao-Chuan CHANG, Ming-Hsiang CHENG, Tsung-Yueh TSAI, Yi-Shao LAI, Ming-Kun CHEN
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Patent number: D1017882Type: GrantFiled: February 21, 2023Date of Patent: March 12, 2024Assignee: JIAXING SUPER LIGHTING ELECTRIC APPLIANCE CO., LTDInventors: Tao Jiang, Ming-Bin Wang, Chen-Kun Chen, Dong-Mei Zhang
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Patent number: D1018774Type: GrantFiled: September 21, 2022Date of Patent: March 19, 2024Assignee: HOMEWAY TECHNOLOGY CO., LTD.Inventors: Ming-Kun Chen, Chin-Hsing Hsieh, Tsung-Hsien Hsieh