Abstract: An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads.

Abstract: According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole extending from the upper surface toward the lower surface; an insulating layer located overlying a sidewall of the hole; and a material layer located overlying the sidewall of the hole, wherein the material layer is separated from the upper surface of the substrate by a distance and a thickness of the material layer decreases along a direction toward the lower surface.

Abstract: An embodiment of the invention provides an interposer which includes: a substrate having a first surface and a second surface; a first hole extending from the first surface towards the second surface; a second hole extending from the first surface towards the second surface, wherein a width of the first hole is different from a width of the second hole; an insulating layer located on the substrate and extending onto a sidewall of the first hole and a sidewall of the second hole; and a conducting layer located on the insulating layer on the substrate and extending onto the sidewall of the first hole, wherein there is substantially no conducting layer in the second hole.

Abstract: An embodiment of the invention provides an interposer which includes: a substrate having a first surface and a second surface; a first hole extending from the first surface towards the second surface; a second hole extending from the first surface towards the second surface, wherein a width of the first hole is different from a width of the second hole; an insulating layer located on the substrate and extending onto a sidewall of the first hole and a sidewall of the second hole; and a conducting layer located on the insulating layer on the substrate and extending onto the sidewall of the first hole, wherein there is substantially no conducting layer in the second hole.

Abstract: An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads.

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a surface; a first conducting layer located on the surface; a second conducting layer located on the surface, wherein the first conducting layer and the second conducting layer are electrically insulated from each other; a first reflective layer conformally located on the first conducting layer and at least partially covering a side of the first conducting layer; a second reflective layer conformally located on the second conducting layer and at least partially covering a side of the second conducting layer; and a chip disposed on the surface of the substrate and having at least a first electrode and a second electrode, wherein the first electrode is electrically connected to the first conducting layer, and the second electrode is electrically connected to the second conducting layer.

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a surface; a reflective layer partially covering the surface of the substrate; an insulating layer formed on the surface of the substrate and the reflective layer; a conducting layer formed on the insulating layer, wherein at least a portion of a direct projection of the conducting layer on the surface does not overlap with a direct projection of the reflective layer on the surface, and the conducting layer does not electrically contact with the reflective layer; and a chip disposed on the surface of the chip, wherein the chip has at least an electrode electrically connected to the conducting layer.

Abstract: A light-emitting diode submount includes a base, a through silicon via and a sealing layer. The base has a die side and a back side. The through silicon via penetrates the base to connect the die side and the back side. The through silicon via includes a conoidal-shaped portion converging from the back side toward the die side, and a vertical via portion connects with the conoidal-shaped portion. A sealing layer seals the vertical via portion.

Abstract: According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole extending from the upper surface toward the lower surface; an insulating layer located overlying a sidewall of the hole; and a material layer located overlying the sidewall of the hole, wherein the material layer is separated from the upper surface of the substrate by a distance and a thickness of the material layer decreases along a direction toward the lower surface.