Patents by Inventor Ming Kuo

Ming Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294028
    Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.
    Type: Grant
    Filed: October 25, 2023
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Publication number: 20250132183
    Abstract: The present disclosure provides a wafer chuck including a substrate and a heating/cooling wafer. The substrate includes a first surface facing a wafer to be carried and a second surface opposite to the first surface. The heating/cooling wafer is disposed on the first surface of the substrate and includes a plurality of heating/cooling units arranged in an array. In a direction perpendicular to the first surface, the positions of the heating/cooling units and the positions of a plurality of dies included in the wafer to be carried are corresponded with each other, and the heating/cooling units can heat or cool the corresponding dies individually.
    Type: Application
    Filed: November 23, 2023
    Publication date: April 24, 2025
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Chi Chou, Chung-Ming Kuo, Bo-An Tsai, Shyng-Yeuan Che
  • Patent number: 12284814
    Abstract: The present disclosure provides a semiconductor structure, including a memory region, a logic region adjacent to the memory region, a first magnetic tunneling junction (MTJ) cell and a second MTJ cell over the memory region, and a carbon-based layer over the memory region, wherein the carbon-based layer includes a recess between the first MTJ cell and the second MTJ cell.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: April 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Huang Huang, Keng-Ming Kuo, Hung Cho Wang
  • Publication number: 20250116903
    Abstract: A light emitting device is provided and includes a first substrate, a light blocking element disposed on the first substrate, and a plurality of light emitting diodes. The light blocking element has a first opening, a second opening, and a third opening, wherein the first opening is adjacent to the second opening, the third opening is adjacent to the first opening, and the first opening and the second opening have different areas. One of the light emitting diodes is overlapped with the third opening. The first opening and the second opening are not overlapped with the plurality of light emitting diodes in a normal direction of a surface of the first substrate.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Applicant: InnoLux Corporation
    Inventor: Shu-Ming KUO
  • Publication number: 20250118559
    Abstract: A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Inventors: Jen-Hong Chang, Yuan-Ching Peng, Jiun-Ming Kuo, Kuo-Yi Chao, Chih-Chung Chang, You-Ting Lin, Yen-Po Lin, Chen-Hsuan Liao
  • Patent number: 12266743
    Abstract: A light-emitting unit is provided. The light-emitting unit includes a light-emitting element, a light conversion layer, and a wall. The light conversion layer is disposed on the light-emitting element. The wall covers a sidewall of the light conversion layer and extends to a portion of an upper surface of the light conversion layer.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: April 1, 2025
    Assignee: INNOLUX CORPORATION
    Inventor: Shu-Ming Kuo
  • Publication number: 20250091299
    Abstract: A system for bonding films includes a first film, a second film having a plurality of elements, a bonding roller, and a deformable roller having a deformable outer layer. The stiffness of the second film is less than that of the first film. By using the system, the deformable outer layer of the deformable roller produces enough deformation during bonding films to fill the area not covered by the plurality of elements on the second film. Therefore, the second film without sufficient stiffness and the first film can be bonded with each other to produce a composite film without wrinkles. A method for preparing a composite film using the system is also disclosed.
    Type: Application
    Filed: August 22, 2024
    Publication date: March 20, 2025
    Applicant: PROLOGIUM TECHNOLOGY CO., LTD.
    Inventors: Jhi-Jhong LIN, Chia-Ming LIN, Che-Ming KUO
  • Patent number: 12255102
    Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Lun Chang, Jiun-Ming Kuo, Ji-Yin Tsai, Yuan-Ching Peng
  • Patent number: 12249539
    Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: March 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Wen Shen, Jiun-Ming Kuo, Yuan-Ching Peng, Ji-Xuan Yang, Jheng-Wei Lin, Chien-Hung Chen
  • Publication number: 20250078897
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.
    Type: Application
    Filed: October 5, 2023
    Publication date: March 6, 2025
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Chen Yang Tang, Hsuan Ming Kuo, Shi-Chieh Hsu, Wei Lin
  • Publication number: 20250081502
    Abstract: A semiconductor device comprises an insulating region surrounding an active area having a channel direction and a transverse direction that is transverse to the channel direction. A source region and a drain region are disposed in the active area, and are spaced apart along the channel direction. A channel is disposed in the active area and is interposed between the source region and the drain region. The channel comprises a two-dimensional electron gas (2DEG). A gate line is oriented along the transverse direction and is disposed on the channel and has a gate width in the channel direction. The gate line comprises gate material. A gate line terminus is disposed at each end of the gate line. Each gate line terminus comprises the gate material. Each gate line terminus has a width in the channel direction that is at least 1.2 time the gate width.
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Inventors: Tzu-Wen Shih, Ching-Hua Chiu, Der-Ming Kuo, Meng-Shao Hsieh, Shih-Hsiang Tai
  • Publication number: 20250077792
    Abstract: Embodiments of the disclosed technologies are capable of a training pipeline to fine-tune a machine learning model given a limited set of domain-specific data. The embodiments describe using a first machine learning model to generate a pseudo label associated with a domain-specific training document. The pseudo label comprises a machine-generated text of a content type extracted from the domain-specific training document. The embodiments further describe fine-tuning a second machine learning model using the pseudo label, the domain-specific training document, a first low-rank weight matrix, and a second low-rank weight matrix. The fine-tuned second machine learning model generates text of the content type from a domain-specific document.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Inventors: Xilun Chen, Tzu Ming Kuo, Xiaoqiang Luo, Ilya Dan Melamed, Ji Yan, Peide Zhong
  • Patent number: 12237398
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
  • Publication number: 20250062151
    Abstract: A manufacturing method of an electronic device is disclosed by the present disclosure. The manufacturing method includes providing a plurality of semiconductor elements; performing a packaging process on the plurality of semiconductor elements to form a plurality of packaged semiconductor elements, wherein the packaging process includes disposing a plurality of filling material layers respectively on a sidewall of each of the plurality of semiconductor elements; providing a substrate, wherein the substrate includes a plurality of working areas, and each of the plurality of working areas includes at least one first recess; and disposing the plurality of packaged semiconductor elements in the at least one first recess of each of the plurality of working areas through fluid transfer.
    Type: Application
    Filed: November 3, 2024
    Publication date: February 20, 2025
    Applicant: InnoLux Corporation
    Inventors: Fang-Ying Lin, Kai Cheng, Ming-Chang Lin, Tsau-Hua Hsieh, Jian-Jung Shih, Shu-Ming Kuo
  • Patent number: 12230712
    Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Shan Lu, Chung-I Yang, Kuo-Yi Chao, Wen-Hsing Hsieh, Jiun-Ming Kuo, Chih-Ching Wang, Yuan-Ching Peng
  • Publication number: 20250056851
    Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Jen-Hong Chang, Yi-Hsiu Liu, You-Ting Lin, Chih-Chung Chang, Kuo-Yi Chao, Jiun-Ming Kuo, Yuan-Ching Peng, Sung-En Lin, Chia-Cheng Chao, Chung-Ting Ko
  • Publication number: 20250052044
    Abstract: A bathtub overflow pipe includes an overflow pipe, an adapter and a over. The overflow pipe includes an extending section with an outlet. The adapter is connected to the end face of the extending section of the overflow pipe by bolts. The adapter includes a sleeve and a tab extending radially from one end of the sleeve. The sleeve includes a passage and is inserted into the outlet of the overflow pipe. The tab has a recess formed to its lower edge and communicating with the outlet for drainage. The cover includes a pillar and a rim which has a recessed area. The pillar extends axially from one of two sides of the cover and has a rib. The pillar extends through the passage of the adapter, the rib is slidably engaged with the recessed rail. The cover, the adapter and the overflow pipe can be precisely and easily assembled.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Inventors: KUANG-MING KUO, CHIH-WEI CHEN
  • Publication number: 20250056950
    Abstract: An electronic device includes a first substrate, a second substrate, a circuit layer, a diode element, and a conductive wire. The first substrate has a first surface, a second surface opposite to the first surface, and a first side surface connected between the first surface and the second surface. The second substrate has a third surface, a fourth surface opposite to the third surface, and a second side surface connected between the third surface and the fourth surface, wherein the fourth surface is disposed away from the first surface. The circuit layer and the diode element are disposed on the first surface. The diode element and the conductive wire are electrically connected to the circuit layer. A first portion of the conductive wire is disposed on the first side surface, and a second portion of the conductive wire is disposed on the second side surface.
    Type: Application
    Filed: October 27, 2024
    Publication date: February 13, 2025
    Applicant: InnoLux Corporation
    Inventors: Wan-Ling Huang, Shu-Ming Kuo, Tsau-Hua Hsieh, Tzu-Min Yan
  • Patent number: 12224183
    Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: February 11, 2025
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Shrane-Ning Jenq, Wen-Cheng Hsu, Chen-Yu Wang, Chih-Ming Kuo, Chwan-Tyaw Chen, Lung-Hua Ho
  • Publication number: 20250044643
    Abstract: A display device is provided, and includes a substrate and a first light shielding layer disposed on the substrate and defining a plurality of first openings. The display device includes a first light filter layer disposed in one of the first openings and a plurality of light-emitting diodes disposed on the substrate. The display device includes a second light shielding layer disposed between the substrate and the first light shielding layer, and having a plurality of second openings. The at least part of the light-emitting diodes are disposed in the second openings respectively. The display device also includes a spacer element disposed between the first light shielding layer and the second light shielding layer, wherein from a cross-section view, a shape of the spacer element is arc-shaped, and a shape of the second light shielding layer is arc-shaped.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Yi-An CHEN, Kuan-Hung KUO, Tsau-Hua HSIEH, Ming-I CHAO, Shu-Ming KUO, Chin-Lung TING, Chih-Yung HSIEH