Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.

Abstract: A method for manufacturing an electronic device is provided. The method includes providing a first substrate. The method further includes forming a bank layer on the first substrate. The bank layer includes a bank wall and a first opening, and the first opening adjacent to the bank wall. The method further includes forming a light conversion layer in the first opening. The method further includes forming a spacer on the bank wall. The method further includes providing a second substrate. The method further includes transferring a plurality of electronic units to the second substrate. The method further includes overlapping the first substrate and second substrate, so that the spacer is located between the first substrate and the second substrate.

Abstract: A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.

Abstract: A system for bonding films includes a first film, a second film having a plurality of elements, a bonding roller, and a deformable roller having a deformable outer layer. The stiffness of the second film is less than that of the first film. By using the system, the deformable outer layer of the deformable roller produces enough deformation during bonding films to fill the area not covered by the plurality of elements on the second film. Therefore, the second film without sufficient stiffness and the first film can be bonded with each other to produce a composite film without wrinkles. A method for preparing a composite film using the system is also disclosed.

Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.

Abstract: An optical beam splitter includes a multi-stage nested network of waveguide bifurcation branches, which includes: first-stage waveguide bifurcation branches each including a pair of first-stage waveguide segments, and second-stage waveguide bifurcation branches each including a pair of second-stage waveguide segments. Each pair of first-stage waveguide segments includes a first common end and a pair of first split ends and a pair of first interconnection portions. Each first common end points toward a first widthwise direction. Each pair of second-stage waveguide segments includes a second common end and a pair of second split ends and a pair of second interconnection portions. Each second common end and each second split end of the optical beam splitter point toward a second widthwise direction which is an opposite direction of the first widthwise direction.

Abstract: In one example in accordance with the present disclosure, an example computing device is disclosed. The example computing device includes a housing. The example computing device also includes a rotatable antenna disposed within the housing. The rotatable antenna is to rotate such that a direction of radiation is maintained in a single direction as the housing is to rotate.

Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

Abstract: Embodiments of the disclosed technologies are capable of a training pipeline to fine-tune a machine learning model given a limited set of domain-specific data. The embodiments describe using a first machine learning model to generate a pseudo label associated with a domain-specific training document. The pseudo label comprises a machine-generated text of a content type extracted from the domain-specific training document. The embodiments further describe fine-tuning a second machine learning model using the pseudo label, the domain-specific training document, a first low-rank weight matrix, and a second low-rank weight matrix. The fine-tuned second machine learning model generates text of the content type from a domain-specific document.

Abstract: A semiconductor device comprises an insulating region surrounding an active area having a channel direction and a transverse direction that is transverse to the channel direction. A source region and a drain region are disposed in the active area, and are spaced apart along the channel direction. A channel is disposed in the active area and is interposed between the source region and the drain region. The channel comprises a two-dimensional electron gas (2DEG). A gate line is oriented along the transverse direction and is disposed on the channel and has a gate width in the channel direction. The gate line comprises gate material. A gate line terminus is disposed at each end of the gate line. Each gate line terminus comprises the gate material. Each gate line terminus has a width in the channel direction that is at least 1.2 time the gate width.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first fin and a gate electrode. The first fin extends along a first direction. The gate electrode has a sidewall extending along a second direction different from the first direction. The sidewall of the gate electrode defines an indentation adjacent to the first fin in a top view.

Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.

Abstract: A bathtub overflow pipe includes an overflow pipe, an adapter and a over. The overflow pipe includes an extending section with an outlet. The adapter is connected to the end face of the extending section of the overflow pipe by bolts. The adapter includes a sleeve and a tab extending radially from one end of the sleeve. The sleeve includes a passage and is inserted into the outlet of the overflow pipe. The tab has a recess formed to its lower edge and communicating with the outlet for drainage. The cover includes a pillar and a rim which has a recessed area. The pillar extends axially from one of two sides of the cover and has a rib. The pillar extends through the passage of the adapter, the rib is slidably engaged with the recessed rail. The cover, the adapter and the overflow pipe can be precisely and easily assembled.

Abstract: An electronic device includes a first substrate, a second substrate, a circuit layer, a diode element, and a conductive wire. The first substrate has a first surface, a second surface opposite to the first surface, and a first side surface connected between the first surface and the second surface. The second substrate has a third surface, a fourth surface opposite to the third surface, and a second side surface connected between the third surface and the fourth surface, wherein the fourth surface is disposed away from the first surface. The circuit layer and the diode element are disposed on the first surface. The diode element and the conductive wire are electrically connected to the circuit layer. A first portion of the conductive wire is disposed on the first side surface, and a second portion of the conductive wire is disposed on the second side surface.

Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.

Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.