Patents by Inventor Ming Kuo
Ming Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250118559Abstract: A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.Type: ApplicationFiled: December 17, 2024Publication date: April 10, 2025Inventors: Jen-Hong Chang, Yuan-Ching Peng, Jiun-Ming Kuo, Kuo-Yi Chao, Chih-Chung Chang, You-Ting Lin, Yen-Po Lin, Chen-Hsuan Liao
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Publication number: 20250116903Abstract: A light emitting device is provided and includes a first substrate, a light blocking element disposed on the first substrate, and a plurality of light emitting diodes. The light blocking element has a first opening, a second opening, and a third opening, wherein the first opening is adjacent to the second opening, the third opening is adjacent to the first opening, and the first opening and the second opening have different areas. One of the light emitting diodes is overlapped with the third opening. The first opening and the second opening are not overlapped with the plurality of light emitting diodes in a normal direction of a surface of the first substrate.Type: ApplicationFiled: December 17, 2024Publication date: April 10, 2025Applicant: InnoLux CorporationInventor: Shu-Ming KUO
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Patent number: 12269732Abstract: A micro-electro-mechanical system (MEMS) microphone is provided. The MEMS microphone includes a substrate, a backplate, an insulating layer, and a diaphragm. The substrate has an opening portion. The backplate is disposed on a side of the substrate, with protrusions protruding toward the substrate. The diaphragm is movably disposed between the substrate and the backplate and spaced apart from the backplate by a spacing distance. The protrusions are configured to limit the deformation of the diaphragm when air flows through the opening portion.Type: GrantFiled: December 30, 2021Date of Patent: April 8, 2025Assignee: FORTEMEDIA, INC.Inventors: Jien-Ming Chen, Chih-Yuan Chen, Feng-Chia Hsu, Wen-Shan Lin, Nai-Hao Kuo
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Publication number: 20250110360Abstract: An embodiment photonic device may include a first terminal including silicon and a second terminal including polysilicon. The first terminal may be configured as a first three-dimensional structure extending along a first direction and having a first U-shaped portion in a first cross-sectional plane perpendicular to the first direction. Similarly, the second terminal may be configured as a second three-dimensional structure extending along the first direction and having a second U-shaped portion in the first cross-sectional plane. The photonic device may further include a capacitor dielectric layer disposed between the first terminal and the second terminal and a cladding dielectric layer surrounding the first terminal and the second terminal. The first U-shaped portion and the second U-shaped portion may be arranged in an interlocking configuration having an overlapping region that is configured as an optical transmission line in which the first direction is an optical propagation direction.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Tien-Lin Shen, Ming Lee, Wei-Heng Lin, Hsing-Kuo Hsia, Chen-Hua Yu
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Publication number: 20250110331Abstract: A lens assembly and Augmented Reality (AR) glasses, including a waveguide substrate, a wiring layer, a protective layer, an eye tracking component, and a lens. The waveguide substrate includes a first surface. The wiring layer is disposed on the first surface. The protective layer is disposed on the first surface and covering the wiring layer. The eye tracking component is disposed in the protective layer and is electrically connected with the wiring layer for tracking position of an eyeball. The lens is connected to a side of the protective layer away from the waveguide substrate. The AR glasses includes a display device and two lens assemblies. The display device is positioned between the two lens assemblies for emitting image light to the waveguide substrates of the two lens assemblies.Type: ApplicationFiled: December 29, 2023Publication date: April 3, 2025Inventors: SHIUE-LUNG CHEN, Chien-Cheng Kuo, I-Ming Cheng, Chang-Ho Chen, Ying-Hung Tsai, Chung-Wu Liu
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Patent number: 12267036Abstract: A method for controlling fans arranged in different working areas comprises: presetting a plurality of fan operation frequencies, receiving a fan operation request and adjusting a frequency of a pulse width modulation (PWM) controller to a first objective frequency based on the fan operation request, and sending the first objective frequency to the fans arranged in different working areas, to drive a first fan arranged in a first objective working area to run. Each of the plurality of fan operation frequencies corresponds to different working areas, the first objective frequency is one of the plurality of fan operation frequencies, and the first objective working area is one of the plurality of working areas corresponding to the first objective frequency. A system for controlling fans and an electronic device are also disclosed.Type: GrantFiled: August 18, 2023Date of Patent: April 1, 2025Assignees: CHAMP TECH OPTICAL (FOSHAN) CORPORATION, Foxconn Technology Co., Ltd.Inventors: Kuan-Ming Wang, Yung-Ping Lin, Po-Tsun Kuo
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Patent number: 12266743Abstract: A light-emitting unit is provided. The light-emitting unit includes a light-emitting element, a light conversion layer, and a wall. The light conversion layer is disposed on the light-emitting element. The wall covers a sidewall of the light conversion layer and extends to a portion of an upper surface of the light conversion layer.Type: GrantFiled: June 5, 2023Date of Patent: April 1, 2025Assignee: INNOLUX CORPORATIONInventor: Shu-Ming Kuo
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Patent number: 12261126Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.Type: GrantFiled: January 24, 2024Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Hsien Chiang, Hsien-Ming Tu, Hao-Yi Tsai, Tin-Hao Kuo
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Publication number: 20250091299Abstract: A system for bonding films includes a first film, a second film having a plurality of elements, a bonding roller, and a deformable roller having a deformable outer layer. The stiffness of the second film is less than that of the first film. By using the system, the deformable outer layer of the deformable roller produces enough deformation during bonding films to fill the area not covered by the plurality of elements on the second film. Therefore, the second film without sufficient stiffness and the first film can be bonded with each other to produce a composite film without wrinkles. A method for preparing a composite film using the system is also disclosed.Type: ApplicationFiled: August 22, 2024Publication date: March 20, 2025Applicant: PROLOGIUM TECHNOLOGY CO., LTD.Inventors: Jhi-Jhong LIN, Chia-Ming LIN, Che-Ming KUO
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Publication number: 20250098410Abstract: A method for manufacturing an electronic device is provided. The method includes providing a first substrate. The method further includes forming a bank layer on the first substrate. The bank layer includes a bank wall and a first opening, and the first opening adjacent to the bank wall. The method further includes forming a light conversion layer in the first opening. The method further includes forming a spacer on the bank wall. The method further includes providing a second substrate. The method further includes transferring a plurality of electronic units to the second substrate. The method further includes overlapping the first substrate and second substrate, so that the spacer is located between the first substrate and the second substrate.Type: ApplicationFiled: August 15, 2024Publication date: March 20, 2025Inventors: Chih-Ming LIANG, Yi-An CHEN, Feng-Yu LIN, Chiung-Chieh KUO
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Publication number: 20250095975Abstract: A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.Type: ApplicationFiled: November 26, 2024Publication date: March 20, 2025Inventors: Tsung-Han KUO, Po-Shu WANG, Wei-Ming WANG
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Patent number: 12255102Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.Type: GrantFiled: November 30, 2023Date of Patent: March 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Che-Lun Chang, Jiun-Ming Kuo, Ji-Yin Tsai, Yuan-Ching Peng
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Publication number: 20250085474Abstract: An optical beam splitter includes a multi-stage nested network of waveguide bifurcation branches, which includes: first-stage waveguide bifurcation branches each including a pair of first-stage waveguide segments, and second-stage waveguide bifurcation branches each including a pair of second-stage waveguide segments. Each pair of first-stage waveguide segments includes a first common end and a pair of first split ends and a pair of first interconnection portions. Each first common end points toward a first widthwise direction. Each pair of second-stage waveguide segments includes a second common end and a pair of second split ends and a pair of second interconnection portions. Each second common end and each second split end of the optical beam splitter point toward a second widthwise direction which is an opposite direction of the first widthwise direction.Type: ApplicationFiled: September 8, 2023Publication date: March 13, 2025Inventors: Chun-Hao Fann, Ming Lee, Wei-Heng Lin, Hsing-Kuo Hsia, Chen-Hua Yu
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Patent number: 12249770Abstract: In one example in accordance with the present disclosure, an example computing device is disclosed. The example computing device includes a housing. The example computing device also includes a rotatable antenna disposed within the housing. The rotatable antenna is to rotate such that a direction of radiation is maintained in a single direction as the housing is to rotate.Type: GrantFiled: October 15, 2020Date of Patent: March 11, 2025Assignee: Hewlett-Packard Development Company, L.P.Inventors: Chun-Chih Liu, Cheng-Ming Lin, Ren-Hao Chen, Chia Hung Kuo
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Patent number: 12249539Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.Type: GrantFiled: June 7, 2022Date of Patent: March 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Wen Shen, Jiun-Ming Kuo, Yuan-Ching Peng, Ji-Xuan Yang, Jheng-Wei Lin, Chien-Hung Chen
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Publication number: 20250078897Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.Type: ApplicationFiled: October 5, 2023Publication date: March 6, 2025Applicant: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Chen Yang Tang, Hsuan Ming Kuo, Shi-Chieh Hsu, Wei Lin
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Publication number: 20250081508Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first fin and a gate electrode. The first fin extends along a first direction. The gate electrode has a sidewall extending along a second direction different from the first direction. The sidewall of the gate electrode defines an indentation adjacent to the first fin in a top view.Type: ApplicationFiled: January 19, 2024Publication date: March 6, 2025Inventors: Yuan Tsung TSAI, Yao Jui KUO, Chia-Wei FAN, Ying Ming WANG, Shih-Hao CHEN, Ling-Sung WANG
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Publication number: 20250081502Abstract: A semiconductor device comprises an insulating region surrounding an active area having a channel direction and a transverse direction that is transverse to the channel direction. A source region and a drain region are disposed in the active area, and are spaced apart along the channel direction. A channel is disposed in the active area and is interposed between the source region and the drain region. The channel comprises a two-dimensional electron gas (2DEG). A gate line is oriented along the transverse direction and is disposed on the channel and has a gate width in the channel direction. The gate line comprises gate material. A gate line terminus is disposed at each end of the gate line. Each gate line terminus comprises the gate material. Each gate line terminus has a width in the channel direction that is at least 1.2 time the gate width.Type: ApplicationFiled: November 19, 2024Publication date: March 6, 2025Inventors: Tzu-Wen Shih, Ching-Hua Chiu, Der-Ming Kuo, Meng-Shao Hsieh, Shih-Hsiang Tai
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Publication number: 20250077792Abstract: Embodiments of the disclosed technologies are capable of a training pipeline to fine-tune a machine learning model given a limited set of domain-specific data. The embodiments describe using a first machine learning model to generate a pseudo label associated with a domain-specific training document. The pseudo label comprises a machine-generated text of a content type extracted from the domain-specific training document. The embodiments further describe fine-tuning a second machine learning model using the pseudo label, the domain-specific training document, a first low-rank weight matrix, and a second low-rank weight matrix. The fine-tuned second machine learning model generates text of the content type from a domain-specific document.Type: ApplicationFiled: August 31, 2023Publication date: March 6, 2025Inventors: Xilun Chen, Tzu Ming Kuo, Xiaoqiang Luo, Ilya Dan Melamed, Ji Yan, Peide Zhong
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Publication number: 20250069975Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.Type: ApplicationFiled: November 12, 2024Publication date: February 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-An Kuo, Ching-Jung Yang, Hsien-Wei Chen, Jie Chen, Ming-Fa Chen