Abstract: A semiconductor structure includes fins protruding from a substrate and separated by a dielectric layer, each semiconductor fin including a plurality of semiconductor layers, source/drain (S/D) features disposed in the semiconductor fins, a first metal gate stack and a second metal gate stack disposed over the semiconductor fins and adjacent to the S/D features, where the first and the second metal gate stacks each include a top portion and a bottom portion disposed below the top portion, and where the bottom portion is interleaved with the semiconductor layers, and an isolation feature disposed on the dielectric layer and in contact with a sidewall surface of each of the first and the second metal gate stacks, where the isolation feature protrudes from the top portion of the first and the second metal gate stack, and where the isolation feature includes two compositionally different dielectric layers.

Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes a chemical formula of MaXbLc, where M is a metal, X is a multidentate aromatic ligand that includes a pyrrole-like nitrogen and a pyridine-like nitrogen, L is an extreme ultraviolet (EUV) cleavable ligand, a is between 1 and 2, b is equal to or greater than 1, and c is equal to or greater than 1.

Abstract: An optical device and method of manufacture is presented. In embodiments a method includes forming a first layer of optical material, patterning the first layer into a stair-step pattern, depositing a dielectric material onto the stair-step pattern, and forming a second layer of optical material over the dielectric material and at least partially within the stair-step pattern.

Abstract: A display device and a fixing structure set are provided. The display device includes a middle frame and a display panel. The middle frame has a first surface and a second surface opposite to the first surface. The display panel is fixed on the first surface by using at least one first fixing structure set and a plurality of second fixing structure sets. Wherein, the fixing structure of the first fixing structure set is different from the fixing structure of the second fixing structure set.

Abstract: An optical device and methods of manufacturing such optical devices are presented. In embodiments the optical device is a tunable beam splitter which is made by forming a first dopant region over a substrate, the first dopant region comprising a first waveguide and a second waveguide, depositing a cladding material over the first waveguide and the second waveguide, and forming a second dopant region overlying the first waveguide and the second waveguide, wherein the forming the second dopant region comprises forming a first region extending over both the first waveguide and the second waveguide, the first region having a constant concentration of a first dopant.

Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.

Abstract: A semiconductor device includes a plurality of intermediate waveguides. The plurality of intermediate waveguides are vertically disposed on top of one another, and vertically adjacent ones of the plurality of intermediate waveguides are laterally offset from each other. When viewed from the top, each of the plurality of intermediate waveguides essentially consists of a first portion and a second portion, the first portion has a first varying width that increases from a first end of the corresponding intermediate waveguide to a middle of the corresponding intermediate waveguide, and the second portion has a second varying width that decreases from the middle of the corresponding intermediate waveguide to a second end of the corresponding intermediate waveguide.

Abstract: A method of the present disclosure includes forming a fin-shaped structure including a plurality of semiconductor layers, a first hard mask layer, a second hard mask layer, and a third hard mask layer, forming a patterned masking layer having a mask portion and a window portion, wherein the third hard mask layer is exposed through the window portion, performing a first etch process to expose the second hard mask layer through the window portion, performing a second etch process to etch the exposed second hard mask layer and to leave behind second hard mask layer residues, performing a third etch process to remove the second hard mask layer residues, etching the plurality of semiconductor layers in the fin-shaped structure through the window portion to divide the fin-shaped structure into a first segment and a second segment, and forming an isolation feature around the first segment and the second segment.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: A method includes forming a first fin structure and a second fin structure protruding from a substrate, forming a dielectric fin between the first fin structure and the second fin structure, recessing the dielectric fin to form a trench between the first fin structure and the second fin structure, and depositing a first dielectric layer on sidewall surfaces of the trench and on a top surface of the recessed dielectric fin. After the depositing the first dielectric layer, a second dielectric layer is deposited in the trench. The method further includes depositing a third dielectric layer to cap the second dielectric layer in the trench, and forming a gate structure on the first fin structure, the second fin structure, and the third dielectric layer.

Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.

Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.

Abstract: An electronic device and a power management method thereof are provided. The power management method includes: detecting a plurality of status information of a plurality of operation statuses of a battery set; determining an information value range within which each of the status information of each of the operation statuses falls, calculating a weighting value of each of the operation statuses according to the information value range; and calculating a weighting value sum corresponding to the weighting values of the operation statuses to set a load capacity of the battery set according to the weighting value sum.

Abstract: A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.

Abstract: The embodiments of the disclosure provide a FinFET. The FinFET includes a substrate, a first gate stack and a second gate stack. The substrate has a first fin and a second fin. The first gate stack is across the first fin and extends along a widthwise direction of the first fin. The second gate stack is across the second fin and extends along a widthwise direction of the second fin. A bottommost surface of the first gate stack is lower than a bottommost surface of the second gate stack, and a first gate height of the first gate stack directly on the first fin is substantially equal to a second gate height of the second gate stack directly on the second fin.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

Abstract: A pill dispensing system includes a tamper resistant top module, an outer case, and a bottom module. The top module includes a locking mechanism configured to lock and unlock the top module. A removable first inner container module includes a pill storage compartment configured to contain a plurality of pills. The removable first inner container module is disposed in a second inner container module positioned in the outer case. The bottom module includes a gate and pill dispensing mechanism. The pill dispensing mechanism is configured to dispense a pill through the gate at a scheduled time configured by a microcontroller. The length of the pill dispensing system is less than twice a diameter of the outer case.

Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate. The backplate comprises a backplate conductive layer and a backplate insulating layer stacked with each other. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The MEMS structure further includes a pillar structure connected with the backplate. The pillar structure comprises a pillar conductive layer and a pillar insulating layer stacked with each other.

Abstract: Methods, systems, and apparatuses are provided to automatically reconstruct an image, such as a 3D image. For example, a computing device may obtain an image, and may apply a first trained machine learning process to the image to generate coefficient values characterizing the image in a plurality of dimensions. Further, the computing device may generate a mesh based on the coefficient values. The computing device may apply a second trained machine learning process to the coefficient values and the image to generate a displacement map. Based on the mesh and the displacement map, the computing device may generate output data characterizing an aligned mesh. The computing device may store the output data within a data repository. In some examples, the computing device provides the output data for display.

Abstract: A semiconductor device includes a pair of fin structures on a semiconductor substrate, each including a vertically stacked plurality of channel layers, a dielectric fin extending in parallel to and between the fin structures, and a gate structure on and extending perpendicularly to the fin structures, the gate structure engaging with the plurality of channel layers. The dielectric fin includes a fin bottom and a fin top over the fin bottom. The fin bottom has a top surface extending above a bottom surface of a topmost channel layer. The fin top includes a core and a shell, the core having a first dielectric material, the shell surrounding the core and having a second dielectric material different from the first dielectric material.