Abstract: Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.

Abstract: Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.

Abstract: Legacy bus operations, such as x86 I/O instructions having an address space separate from memory address space, are supported in a system in which I/O devices are coupled to a microcontroller connected via an SPI bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus. Existing software infrastructure using x86 I/O instructions can remain intact, with I/O transactions bound for the SPI bus.

Abstract: A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.

Abstract: A circuit for use in a computing system including a bus interface unit and an autoload controller. The autoload controller has an input to receive an initialization signal. In response to receiving the initialization signal, the autoload controller searches for a signature using the bus interface unit and, in response to finding the signature at a signature address, loads a plurality of base addresses corresponding to a plurality of controllers from memory locations having a predetermined relationship to the address, and provides the plurality of base addresses to a control output thereof.

Abstract: Current computer systems support sleep states such as sleep state S3 and sleep state S4. A system in sleep state S3 utilizes more power than one in sleep state S4, however, a system in sleep state S3 can resume function substantially faster than a system in sleep state S4. An idle system is often put into sleep state S3 rather than sleep state S4 because of the shorter resume time even though sleep state S3 utilizes more power. Embodiments include a reduced-power sleep state S3 that uses less power than sleep state S3 yet resumes function faster than sleep state S4. Embodiments reduce the power consumed by compressing and consolidating system context to fewer memory modules, and powering down unused memory modules. Embodiments thus avoid storing system content to non-volatile memory. Embodiments include waking the system by restoring system context in the reverse order to respective memory modules.

Abstract: Methods and apparatus for dynamically adjusting a power level of an electronic device (100) are disclosed. In an embodiment, an electronic device (100) receives a usage pattern of the electronic device (100) (e.g., typically used 9:00 AM to 5:00 PM on weekdays). The electronic device (100) then dynamically adjusts a wake up timer (204) associated with the electronic device (100) based on the usage pattern (e.g., expire at 8:50 am the next morning, which is 10 minutes before usage typically resumes for that day). In response to an expiration of the dynamically adjusted wake up timer (204), the electronic device (100) increases the power level of the electronic device (100) (e.g., transition from hibernate mode to standby mode, possibly via other intervening power modes, for faster startup in anticipation of resumed usage).

Abstract: Legacy bus operations, such as x86 I/O instructions having an address space separate from memory address space, are supported in a system in which I/O devices are coupled to a microcontroller connected via an SPI bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus. Existing software infrastructure using x86 I/O instructions can remain intact, with I/O transactions bound for the SPI bus.

Abstract: A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.

Abstract: A circuit for use in a computing system including and a bus interface unit and an autoload controller. The autoload controller has an input to receive an initialization signal. In response to receiving the initialization signal, autoload controller searches for a signature using the bus interface unit and, in response to finding the signature at a signature address, loads a plurality of base addresses corresponding to a plurality of controllers from memory locations having a predetermined relationship to the address, and provides the plurality of base addresses to a control output thereof.

Abstract: A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.

Abstract: Embodiments of a method and system for conserving power used in a central processing unit (CPU) are described. An embodiment uses direct memory access (DMA) fetch suspend logic to allow the CPU to stay in a sleep state indefinitely until a break event occurs. Embodiments include power management monitoring and Universal Serial Bus (USB) descriptor monitoring logic. Power management monitor logic monitors the CPU sleep state and sets a status flag to the USB descriptor monitoring logic whenever the CPU is in a predefined sleep state. The USB descriptor monitoring logic monitors the fetching of linked descriptor lists. When the CPU status flag is raised, it causes monitoring of the descriptor fetch by the USB descriptor monitoring logic. If the USB controller has completed all of the descriptor fetches while the CPU sleep flag is true, this logic sets a flag to cause the USB controller to suspend DMA fetch operations.

Abstract: A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.

Abstract: Embodiments of a method and system for conserving power used in a central processing unit (CPU) are described. An embodiment uses direct memory access (DMA) fetch suspend logic to allow the CPU to stay in a sleep state indefinitely until a break event occurs. Embodiments include power management monitoring and Universal Serial Bus (USB) descriptor monitoring logic. Power management monitor logic monitors the CPU sleep state and sets a status flag to the USB descriptor monitoring logic whenever the CPU is in a predefined sleep state. The USB descriptor monitoring logic monitors the fetching of linked descriptor lists. When the CPU status flag is raised, it causes monitoring of the descriptor fetch by the USB descriptor monitoring logic. If the USB controller has completed all of the descriptor fetches while the CPU sleep flag is true, this logic sets a flag to cause the USB controller to suspend DMA fetch operations.