Abstract: A parallel processing decision feedback equalizer is configured to receive a plurality of symbol blocks in parallel via a plurality of corresponding input branches. It is further configured to generate a plurality of decision samples. The equalizer comprises an input buffer for storing calculated decision samples corresponding to at least one previously received symbol block and a plurality of tapped delay calculators coupled to the input buffer and located in each of the input branches which are configured to calculate the first portion of a decision feedback signal corresponding to each input branch based on the impulse response samples and the decision samples stored in said input buffer. A plurality of look-ahead-processors located in each one of the input branches and is coupled to a corresponding one of the tapped delay calculators.