Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.

Abstract: A sewing machine includes a main body and a quick release needle plate module. The main body includes a base seat having an inner frame, and an outer case that is mounted to the inner frame and that defines an accommodating compartment. The quick release needle plate module includes a catch member, and a needle plate that covers the accommodating compartment, that is detachably pivoted to a rear section of the inner frame, and that engages the catch member. The quick release needle plate module further includes a press member inserted through the outer case and the inner frame, and operable to push the catch member to disengage the catch member. The needle plate has a plate body that covers the accommodating compartment, and a resilient member mounted between the inner frame and the plate body for driving pivot action of the plate body away from the inner frame.

Abstract: A method for manufacturing a semiconductor structure includes forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature; forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material; forming a second dielectric feature with a first opening that exposes the first cap element; forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer; removing a portion of the first cap element exposed from the barrier layer; and forming a second conductive element in the first opening.

Abstract: A solder joint inspection model training method includes the steps of: training a first identification model according to first sample images to identify a surface-mount device with a solder joint in an image; training a second identification model according to second sample images to identify a surface-mount device without a solder joint in an image; inputting labeled original images to a trained first identification model to output first images; inputting the first images to a trained second identification model to output second images; masking the first images with the second images to generate images with normal solder joints and images with abnormal solder joints; and training a solder joint inspection model based on the images with normal solder joints and the images with abnormal solder joints.

Abstract: A solder joint inspection model training method includes the steps of: training a first identification model according to first sample images to identify a surface-mount device with a solder joint in an image; training a second identification model according to second sample images to identify a surface-mount device without a solder joint in an image; inputting labeled original images to a trained first identification model to output first images; inputting the first images to a trained second identification model to output second images; masking the first images with the second images to generate images with normal solder joints and images with abnormal solder joints; and training a solder joint inspection model based on the images with normal solder joints and the images with abnormal solder joints.

Abstract: A single layer structure of micron or nano fibers, and a multi-layer structure of micron and nano fibers. The single layer structure of micron fibers includes a web of micron fibers and an impregnating resin, and has a pore size of 1 nm-500 nm. The web of micron fibers is formed by plural interweaved micron fibers (D?1 ?m). The single layer structure of nano fibers includes a web of nano fibers formed by plural interweaved nano fibers (D<1 ?m). The multi-layer structure of micron and nano fibers includes a web of interweaved micron fibers, a web of nano fibers formed by plural nano fibers interweaved on the web of micron fibers, a mixture layer formed by parts of the interweaved nano and micron fibers, and a resin at least impregnating the mixture layer and parts of the micron fibers of the web of micron fibers.

Abstract: A single fiber layer structure of micron or nano fibers, and a multi-layer structure of micron and nano fibers are provided. The single fiber layer structure of micron fibers comprises a web of micron fibers and an impregnating resin, and has a pore size of 1 nm-500 nm. The web of micron fibers is formed by plural interweaved micron fibers (D?1 ?m). The single fiber layer structure of nano fibers comprises a web of nano fibers formed by plural interweaved nano fibers (D<1 ?m). The multi-layer structure of micron and nano fibers comprises a web of interweaved micron fibers, a web of nano fibers formed by plural nano fibers interweaved on the web of micron fibers, a mixture layer formed by parts of the interweaved nano and micron fibers, and a resin at least impregnating the mixture layer and parts of the micron fibers of the web of micron fibers.

Abstract: A single fiber layer structure of micron or nano fibers, and a multi-layer structure of micron and nano fibers are provided. The single fiber layer structure of micron fibers comprises a web of micron fibers and an impregnating resin, and has a pore size of 1 nm-500 nm. The web of micron fibers is formed by plural interweaved micron fibers (D?1 ?m). The single fiber layer structure of nano fibers comprises a web of nano fibers formed by plural interweaved nano fibers (D<1 ?m). The multi-layer structure of micron and nano fibers comprises a web of interweaved micron fibers, a web of nano fibers formed by plural nano fibers interweaved on the web of micron fibers, a mixture layer formed by parts of the interweaved nano and micron fibers, and a resin at least impregnating the mixture layer and parts of the micron fibers of the web of micron fibers.

Abstract: A single fiber layer structure of micron or nano fibers, and a multi-layer structure of micron and nano fibers are provided. The single fiber layer structure of micron fibers comprises a web of micron fibers and an impregnating resin, and has a pore size of 1 nm-500 nm. The web of micron fibers is formed by plural interweaved micron fibers (D?1 ?m). The single fiber layer structure of nano fibers comprises a web of nano fibers formed by plural interweaved nano fibers (D<1 ?m). The multi-layer structure of micron and nano fibers comprises a web of interweaved micron fibers, a web of nano fibers formed by plural nano fibers interweaved on the web of micron fibers, a mixture layer formed by parts of the interweaved nano and micron fibers, and a resin at least impregnating the mixture layer and parts of the micron fibers of the web of micron fibers.

Abstract: The present invention discloses a computer motherboard, which comprises: at least one memory module slot, a flash memory, a central processing unit socket; wherein, the memory module slot is used to plug at least one memory module; the flash memory is used to store BIOS programming codes, in which the BIOS programming codes are provided with at least one memory configuration programming codes for configuring the memory frequency and memory timing of the memory module; the central processing unit socket is used to plug the CPU, and the CPU is at least used to execute the memory configuration programming codes, so, after execution, they could provide a plurality of parameter options for memory frequency and memory timing of the memory modules to be selected one from them.

Abstract: A complex input/output port connecter is applied in an electronic device and electrically connected with at least an input/output module. The electrical connecter includes a frame and a plurality of signal lines. The frame accommodates at least one input/output module. The signal lines are arranged on one side of the frame in a direction perpendicular to an assembly direction of the input/output module and electrically connected with a circuit board of the electronic device. The input/output modules are installed within the frame freely according to usage requirements and electrically contact the corresponding signal lines to form an electrical connection.

Abstract: A system for checking and correcting BIOS errors is provided. The system includes a program loading module (1001) for loading main programs from a BIOS ROM into a RAM; a checksum calculating module (1002) for reading the original checksum, and for calculating a new checksum for the main programs loaded in the RAM; an error checking module (1003) determining if the new checksum equals the original checksum; an error checking module for comparing the new checksum with the original checksum to identify errors in the main programs; and an error correcting module (1004) for correcting the errors in the main programs loaded in the RAM. A related method is also disclosed.

Abstract: The present invention discloses a computer motherboard, which comprises: at least one memory module slot, a flash memory, a central processing unit socket, wherein, the memory module slot is used to plug at least one memory module; the flash memory is used to store BIOS programming codes, in which the BIOS programming codes are provided with at least one memory configuration programming codes for configuring the memory frequency and memory timing of the memory module; the central processing unit socket is used to plug the CPU, and the CPU is at least used to execute the memory configuration programming codes, so, after execution, they could provide a plurality of parameter options for memory frequency and memory timing of the memory modules to be selected one from them.

Abstract: A complex input/output port connecter is applied in an electronic device and electrically connected with at least an input/output module. The electrical connecter includes a frame and a plurality of signal lines. The frame accommodates at least one input/output module. The signal lines are arranged on one side of the frame in a direction perpendicular to an assembly direction of the input/output module and electrically connected with a circuit board of the electronic device. The input/output modules are installed within the frame freely according to usage requirements and electrically contact the corresponding signal lines to form an electrical connection.

Abstract: A method for reconfiguring an RTC time of a computer is disclosed. The method includes the steps of: storing an initial real time clock (RTC) time when the computer is powered on; calculating a first elapsed time tracked from the initial RTC time and a second elapsed time tracked from the initial RTC time; reading an RTC time of the computer after a time span of the first elapsed time; detecting whether the RTC time equals the sum of the initial RTC time and the first elapsed time; and adjusting a current RTC time of the computer after a time span of the second elapsed time to the sum of the initial RTC time and the second elapsed time, if the RTC time doesn't equal to the sum of the initial RTC time and the first elapsed time. A related system is also disclosed.

Abstract: An exemplary method for BIOS setup includes the steps of: setting selectable options of device configurations according to parameter ranges of device configurations of the BIOS, each selectable option corresponding to a selection indicator, each selection indicator corresponding to a type of color and an alarm sound; modifying working condition parameters of the device configurations; determining whether the new configuration values are dangerous values; determining the selection indicator according to corresponding selectable options of device configurations if any new configuration value is a dangerous value; and displaying the device configuration with corresponding color, and alarming with the corresponding alarm sound. A related system for BIOS setup is also disclosed.

Abstract: A system for selecting boot devices via hotkeys is disclosed, the system includes: a setting module (301) for setting and saving one or more hotkeys for each bootable device in the computer (20) via a input device (10); a detecting module (302) for detecting whether any hotkeys are pressed during a power on self test (POST); a comparing module (303) for comparing the pressed hotkeys with the preset hotkeys, and determining a target boot device according to the comparison result; and a booting module (304) for booting up the computer (20) from the target boot device. A related method is also disclosed.

Abstract: A computer-based method for selecting a first boot device for a computer is provided. The method includes the steps of: initializing a boot menu, and initializing a time value for the boot menu; entering a POST program and displaying the boot menu; decrementing the time value, and clocking the boot menu; restarting the computer from a first boot device which is selected during the time period according to the time value; and saving parameters of the first boot device into a CMOS. A related system is also disclosed.

Abstract: A system for checking and correcting BIOS errors is provided. The system includes a program loading module (1001) for loading main programs from a BIOS ROM into a RAM; a checksum calculating module (1002) for reading the original checksum, and for calculating a new checksum for the main programs loaded in the RAM; an error checking module (1003) determining if the new checksum equals the original checksum; an error checking module for comparing the new checksum with the original checksum to identify errors in the main programs; and an error correcting module (1004) for correcting the errors in the main programs loaded in the RAM. A related method is also disclosed.

Abstract: An exemplary method for BIOS setup includes the steps of: setting selectable options of device configurations according to parameter ranges of device configurations of the BIOS, each selectable option corresponding to a selection indicator, each selection indicator corresponding to a type of color and an alarm sound; modifying working condition parameters of the device configurations; determining whether the new configuration values are dangerous values; determining the selection indicator according to corresponding selectable options of device configurations if any new configuration value is a dangerous value; and displaying the device configuration with corresponding color, and alarming with the corresponding alarm sound. A related system for BIOS setup is also disclosed.