Abstract: A system for providing video playback comprises a processor configured to synchronize clocks on the plurality of devices to a standard time, provide target video playback positions to the plurality of devices, wherein target video playback positions are based at least in part on the timing information, provide one or more locators for video streams to the plurality of devices, monitor playback status for each of the plurality of devices, and for a device, determine whether the playback status for the device indicates that a selected bitrate is too low or too high or that the playback is fast or slow; in response to determining the selected bitrate is too low, indicate to select a higher bitrate for a device; and in response to determining the selected bitrate is too high, indicate to select a lower bitrate for the device.

Abstract: A system for providing video playback includes an interface and a processor. The interface is configured to receive a desired video playback request and receive a video content source switching request from a first video content source to a second video content source. The processor is configured to generate a not-all-I-frame first stream for the first video content source, generate an all-I-frame second stream and a not-all-I-frame second stream for the second video content source, switch from the not-all-I-frame first stream for the first video content source to the all-I-frame second stream for the second video content source, and switch from the all-I-frame second stream for the second video content source to the not-all-I-frame second stream for the second video content source on a next I-frame occurrence in the not-all-I-frame second stream for the second video content source.

Abstract: A method for multi-threshold voltage CMOS process optimization. The method includes the steps of: providing a semiconductor substrate with a plurality of devices of different threshold voltages; establishing a plurality of types of timing models for a timing calculation; obtaining a static timing analysis report through the timing calculation; defining a large and a small setup time margin as a Tl and a Ts; changing the devices whose setup time margins are less than Ts to low threshold devices; changing the devices whose setup time margins are greater than Tl to high threshold devices; checking a setup time of each device; changing the devices whose setup time margin does not meet the enhanced static timing analysis report; performing a first pocket implant process for the normal threshold devices; performing a second pocket implant process for the low threshold devices and performing a third pocket implant process for the high threshold devices.

Abstract: A method for multi-threshold voltage CMOS process optimization. The method includes the steps of: providing a semiconductor substrate with a plurality of devices of different threshold voltages; establishing a plurality of types of timing models for a timing calculation; obtaining a static timing analysis report through the timing calculation; defining a large and a small setup time margin as a Tl and a Ts; changing the devices whose setup time margins are less than Ts to low threshold devices; changing the devices whose setup time margins are greater than Tl to high threshold devices; checking a setup time of each device; changing the devices whose setup time margin does not meet the enhanced static timing analysis report; performing a first pocket implant process for the normal threshold devices; performing a second pocket implant process for the low threshold devices and performing a third pocket implant process for the high threshold devices.

Abstract: An apparatus and method for controlling an asynchronous dual port FIFO memory is provided. The asynchronous FIFO may operate at frequencies satisfying 0.5f2<f1<f2 or 0.5f1<f2<f1, where f2 is the write frequency if f1 is the read frequency, or vice versa. A FIFO in accordance with the present invention comprises a dual port random access memory, a read pointer, a write pointer, a synchronization circuit and a status indicator. In the FIFO design, the read pointer indicating the read address is a simple sequential counter, and the write pointer indicating the write address is a Gray code counter. Gray code to sequential count converters are used to convert the Gray codes to sequential counts. The synchronization circuit synchronizes the write pointer and the read pointer using a read clock. A status indicator with simple circuits is provided to indicate if the FIFO is almost full or empty.

Abstract: Disclosed is an improved computer graphics memory architecture. The architecture includes an address translation table (ATT) and a buffer. The address translation table receives information about desired pixel data and determines the physical address of the desired data. The buffer is connected to the ATT and has a dual bank which stores the color value and the Z value of a 3-D pixel. A buffer addressing method is also provided in which the address of the desired pixel information and associated control circuits may be quickly determined through an appropriate data arrangement in the buffer and an address transfer table.