Patents by Inventor Ming Pan

Ming Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12319729
    Abstract: The present disclosure provides an anti-Staphylococcus aureus specific antibody and the nucleic acid encoding sequence thereof, and uses of the same. The anti-Staphylococcus aureus specific antibody of the present disclosure achieves the effect of treating Staphylococcus aureus infection and enhancing immune cells against Staphylococcus aureus through various efficacy experiments.
    Type: Grant
    Filed: April 2, 2024
    Date of Patent: June 3, 2025
    Assignee: CHINA MEDICAL UNIVERSITY HOSPITAL
    Inventors: Der-Yang Cho, Shao-Chih Chiu, Shi-Wei Huang, Chih-Ming Pan, Mei-Chih Chen, Yeh Chen, Po-Ren Hsueh, Tien Ni, Jia-Xin Yu, Chao-Jung Chen
  • Patent number: 12317545
    Abstract: A method includes sequentially depositing a floating gate layer, a dielectric structure stack, and a control gate layer over a substrate. A first etching process is performed to pattern the control gate layer, the dielectric structure stack, and a top portion of the floating gate layer to form a control gate, a dielectric structure, and a top portion of a floating gate over a bottom portion of the floating gate layer. A sidewall of the top portion of the floating gate is concave. A first spacer structure is formed on the sidewall of the top portion of the floating gate, a sidewall of the dielectric structure, and a sidewall of the control gate. A second etching process is performed to pattern the bottom portion of the floating gate layer to form a bottom portion of the floating gate after forming the first spacer structure.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Chia-Ming Pan, Su-Yu Yeh, Keng-Ying Liao, Chih-Wei Sung
  • Publication number: 20250167496
    Abstract: A magnetic lock for charging an electric vehicle and an operating method of the magnetic lock are provided. The magnetic lock includes a voltage conversion circuit, a detection circuit, and a magnetic attraction circuit. The voltage conversion circuit receives a first voltage from a power supplying connector and converts the first voltage into a second voltage and a third voltage. The detection circuit is driven according to the second voltage, provides a first control signal according to a first status signal from the power supplying connector, and provides a second control signal according to the second status signal from the power supplying connector. The magnetic attraction circuit uses the third voltage to generate a magnetic attraction force according to the first control signal. The power supplying connector is fixed to a charging port of the electric vehicle by the magnetic attraction force.
    Type: Application
    Filed: February 21, 2024
    Publication date: May 22, 2025
    Applicant: Wistron Corporation
    Inventors: Hsiao Wei Chien, Chien Ming Pan, Ying-Hao Peng, Cheng-Wei Huang, Wen Ju Chen
  • Publication number: 20250093008
    Abstract: A bendable light device for a vehicle is provided and includes a bendable mounting plate and a light kit. The bendable mounting plate includes a main body portion. The light kit includes a first light assembly having a first light base, a first light cover and a first light emitting module between the first light base and the first light cover. A first assembling portion is formed on a side of the first light base and for assembling with the main body portion of the bendable mounting plate. The first light cover is mounted on the first light base. The bendable mounting plate is bent to be attached onto a surface of a vehicle body of the vehicle and fitted with a curve of the surface, such that the bendable light device can be easily attached onto the surface of the vehicle body of the vehicle without any gap therebetween.
    Type: Application
    Filed: September 8, 2024
    Publication date: March 20, 2025
    Applicant: Juluen Enterprise Co., Ltd.
    Inventors: Shuo-Ying Yen, Sheng-Ming Pan
  • Publication number: 20250098227
    Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: Yu-Chu Lin, Chia-Ming Pan, Chi-Chung Jen, Wen-Chih Chiang, Huai-Jen Tung, Keng-Ying Liao
  • Patent number: 12249657
    Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Wen-Chih Chiang, Ming-Hong Su, Yung-Han Chen, Mei-Chen Su, Chia-Ming Pan
  • Publication number: 20250057973
    Abstract: A drug carrier with a property of crossing the blood-brain barrier comprises an extracellular vesicle with a human leukocyte antigen-G antibody on its surface. This carrier can serve as a pharmaceutical composition for promoting apoptosis of brain tumor cells, inhibiting growth of brain tumor cells, or reducing expression of O6-methylguanine-DNA methyltransferase (MGMT) in brain tumor cells. These effects contribute to the treatment of glioblastoma multiforme (GBM).
    Type: Application
    Filed: August 13, 2024
    Publication date: February 20, 2025
    Inventors: Der-Yang Cho, Shao-Chih Chiu, Yi-Wen Chen, Ming-You Shie, Chih-Ming Pan, Shi-Wei Huang, Yen Chen, Cheng-Yu Chen, Kai-Wen Kan
  • Patent number: 12221483
    Abstract: The present disclosure provides a fusion protein and the nucleic acid encoding sequence thereof, and uses of the same. The fusion protein of the present disclosure achieves the effect of treating cancer, immunoregulation and activating immune cells through various efficacy experiments.
    Type: Grant
    Filed: January 30, 2024
    Date of Patent: February 11, 2025
    Assignee: CHINA MEDICAL UNIVERSITY HOSPITAL
    Inventors: Der-Yang Cho, Shao-Chih Chiu, Shi-Wei Huang, Chih-Ming Pan, Mei-Chih Chen, Yu-Chuan Lin, Yeh Chen, Yi-Wen Chen, Ming-You Shie, Kai-Wen Kan
  • Patent number: 12199159
    Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.
    Type: Grant
    Filed: June 19, 2023
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chu Lin, Chia-Ming Pan, Chi-Chung Jen, Wen-Chih Chiang, Huai-Jen Tung, Keng-Ying Liao
  • Publication number: 20250006871
    Abstract: A display device having a wide color gamut includes a backplane, a light emitting group, a protective layer, and a color conversion structure. The light emitting group is disposed on the backplane, and includes a plurality of blue light emitting elements arranged at intervals. The protective layer encapsulates the blue light emitting elements in a lateral direction to expose their light emitting surfaces. The color conversion structure is disposed on the light emitting group to convert light from one portion of the blue light emitting elements into red light and green light and allow light from another one portion of the blue light emitting elements to pass through. The protective layer has a transmittance of 10% or less of light having a wavelength greater than 380 nm and less than 500 nm.
    Type: Application
    Filed: September 13, 2023
    Publication date: January 2, 2025
    Inventors: YU-CHANG HU, Bo-Ren Lin, Hsin-I Lu, SHYI-MING PAN, FENG-HUI CHUANG
  • Publication number: 20240387749
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, Chia-Wei LEE, Kuan-Wei SU, Chia-Ming PAN
  • Publication number: 20240374659
    Abstract: The main objective of the present invention is to provide a lactic acid bacterial strain and a composition for improving gut microbiota composition. The composition comprises the lactic acid bacterial strain and/or extracellular vesicles secreted by the lactic acid bacterial strain. Another objective of the present invention is to provide a method for improving gut microbiota composition and products of the lactic acid bacterial strain. Additionally, the composition of the present invention has the capability to influence the growth of Firmicutes and Bacteroidetes, thereby leading to an improvement in gut microbiota composition.
    Type: Application
    Filed: December 29, 2023
    Publication date: November 14, 2024
    Inventors: TZU-MING PAN, TSUNG-WEI SHIH, WEI-HSUAN HSU
  • Publication number: 20240374726
    Abstract: A BAG6 specific chimeric antigen receptor, a nucleic acid, a BAG6 specific chimeric antigen receptor expression plasmid, a BAG6 specific chimeric antigen receptor expressing cell, a pharmaceutical composition for treating cancer, and use of the BAG6 specific chimeric antigen receptor expressing cell are provided. The BAG6 specific chimeric antigen receptor specifically binds to BCL2 associated athanogene 6 (BAG6). The nucleic acid encodes the BAG6 specific chimeric antigen receptor. The BAG6 specific chimeric antigen receptor expression plasmid expresses the BAG6 specific chimeric antigen receptor. The BAG6 specific chimeric antigen receptor expressing cell is obtained by transducing the BAG6 specific chimeric antigen receptor into an immune cell. The pharmaceutical composition for treating cancer includes the BAG6 specific chimeric antigen receptor expressing cell and a pharmaceutically acceptable carrier.
    Type: Application
    Filed: May 3, 2024
    Publication date: November 14, 2024
    Applicant: China Medical University Hospital
    Inventors: Der-Yang Cho, Shao-Chih Chiu, Chia-Ing Jan, Chih-Ming Pan, Shi-Wei Huang
  • Publication number: 20240379651
    Abstract: An example manufacturing method includes performing first ion implantation into a first area of a substrate to form a buried layer. Second ion implantation into a second area of the substrate is performed to form a pre-dopant, where the second area is disposed around a periphery of the first area, and a thermal diffusion capability of ions in the pre-dopant is higher than a thermal diffusion capability of ions at the buried layer. An epitaxial layer is formed on a side, of the substrate, on which the buried layer and the pre-dopant are disposed. Third ion implantation into the epitaxial layer is performed, in correspondence to the second area, to form a deep well. Thermal annealing is performed to thermally diffuse ions at the buried layer, in the pre-dopant, and in the deep well.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Peng GOU, Can ZHONG, Fengjie TANG, Xiran ZUO, Ming PAN, Liu YUAN, Tianyi ZHANG, Guidong JIN, Yanjun CHEN
  • Publication number: 20240347645
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.
    Type: Application
    Filed: June 24, 2024
    Publication date: October 17, 2024
    Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, Chia-Wei LEE, Kuan-Wei SU, Chia-Ming PAN
  • Publication number: 20240339019
    Abstract: A system for monitoring usage of an electrical appliance includes an electrical socket device and a server. The electrical socket device includes an audio receiving module for generating an audio result based on sound at a site where the electrical appliance is disposed, and a processing module configured to generate audio feature data based on the audio result and to generate event data that is related to the usage of the electrical appliance at least based on the audio feature data. The server stores a behavioral feature recognition model that is configured to recognize multiple behavioral features related to behaviors of the user using the electrical appliance. The server uses the behavioral feature recognition model to determine whether the event data matches one of the behavioral feature, and sends a warning message to a user end device when the event data does not match any of the behavioral features.
    Type: Application
    Filed: June 20, 2024
    Publication date: October 10, 2024
    Inventors: Hui-Ming PAN, Hsiu-Ping CHOU, Hung-Yao WU, Hsin-Yu LI, Chun-Yu MAK
  • Patent number: 12113135
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Wen-Chih Chiang, Chi-Chung Jen, Ming-Hong Su, Mei-Chen Su, Chia-Wei Lee, Kuan-Wei Su, Chia-Ming Pan
  • Patent number: 12100952
    Abstract: A site monitoring method uses an electrical socket device to collect current data of an electrical appliance that is electrically connected to the electrical socket device. Based on the current data, a management server can derive a user behavior in connection with using the electrical appliance, and send out a warning message when the user behavior thus derived is abnormal.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: September 24, 2024
    Assignee: UEC SYSTEM SOLUTIONS CORPORATION
    Inventors: Hui-Ming Pan, Hsiu-Ping Chou, Hung-Yao Wu, Tsung-Fang Tu, Hui-Hsien Wang
  • Publication number: 20240273165
    Abstract: A system, method, and computer program product include: collecting runtime history capture data by a data agent operable on a computing device; performing a pre-analysis of entries in the history capture data, the history capture data including a plurality of database transactions corresponding to user tables, and providing formatted history capture data; clustering the formatted history capture data into clusters by data characteristics of interval groups; performing a post-analysis on the clusters and providing a unit data profile for capture data of the user tables; and dynamically updating capture policies corresponding to capture processes for the user tables, the updating based at least on the unit data profile provided by the post-analysis. In some embodiments the clustering is density based. Optionally, an alert is sent when capture process capacity is exceeded.
    Type: Application
    Filed: February 9, 2023
    Publication date: August 15, 2024
    Inventors: Bo Chen ZHU, Mai ZENG, Xin Xin DONG, Ming Qiao SHANG GUAN, Wei SONG, Tian Ming PAN, Wen Zhong LIU
  • Patent number: 12051755
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Wen-Chih Chiang, Chi-Chung Jen, Ming-Hong Su, Mei-Chen Su, Chia-Wei Lee, Kuan-Wei Su, Chia-Ming Pan