Patents by Inventor Ming Peng

Ming Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12332555
    Abstract: An optical engine module used in a projection device and configured to generate an image beam includes a housing and a plate. The housing has a surrounding side wall and a bottom wall connected to each other. The bottom wall has a first opening. The surrounding side wall has an off-state beam irradiation zone adjacent to the first opening. The first opening is configured to allow the image beam to exit. The off-state beam irradiation zone is configured to be irradiated by an off-state beam. The plate has a light receiving part and a heat dissipating part. The light receiving part is disposed in the off-state beam irradiation zone. The heat dissipating part passes through the bottom wall and extends out of the housing. A projection device adopting the optical engine module is also provided.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: June 17, 2025
    Assignee: Coretronic Corporation
    Inventors: Mao-Min Fu, Chien-Ming Peng
  • Patent number: 12238864
    Abstract: An electronic apparatus including a compression molding board and a connection pad is provided. The compression molding board has a device bonding area and a bending area formed by compression molding. The device bonding area is different from the bending area. The connection pad is disposed on the device bonding area of the compression molding board.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: February 25, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Lin Hsu, Kuan-Chu Wu, Ting-Yu Ke, Min-Hsiung Liang, Yu-Ming Peng
  • Patent number: 12231751
    Abstract: A modular omni-directional sensor array (MOSA) enclosure is provided for visual surveillance. The MOSA enclosure is disposable on an elevated position and includes a lower equipment module and an upper optical module. The equipment module contains electrical power and control electronics and is disposed on the elevated position from underneath. The optical module contains a plurality of cameras viewing radially outward. The optical module is disposed onto the equipment module from above.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: February 18, 2025
    Assignee: United States of America, represented by the Secretary of the Navy
    Inventors: Timothy Li-Ming Peng, Eric Wayne Stacy, David Bone Clark, III
  • Patent number: 12211811
    Abstract: An electronic device includes a substrate, an electronic component, a first interposing layer and a second interposing layer. The substrate is non-planar and the substrate includes a first substrate pad and a second substrate pad. The electronic component includes a first component pad and a second component pad corresponding to the first substrate pad and the second substrate pad respectively. When the first component pad contacts the first substrate pad, a height difference exists between the second component pad and the second substrate pad. The first interposing layer connects between the first component pad and the first substrate pad. The second interposing layer connects between the second component pad and the second substrate pad. A thickness difference between the first interposing layer and the second interposing layer is 0.5 to 1 time the height difference.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: January 28, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Ming Peng, Chien-Chou Tseng, Chih-Chia Chang, Kuan-Chu Wu, Yu-Lin Hsu
  • Patent number: 12119403
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Patent number: 12089326
    Abstract: A double-sided flexible circuit board includes a flexible substrate, through circuit lines, first circuit lines and second circuit lines. The first circuit lines are formed on a top surface of the flexible substrate and each includes a first segment, a bent segment and a second segment. One end of the first segment is connected to a first connection end of one of the through circuit lines. Both ends of the bent segment are connected to the other end of the first segment and one end of the second segment, respectively. A second distance between the adjacent second segments is greater than a first distance between the adjacent first segments. The second circuit lines are formed on a bottom surface of the flexible substrate and each is connected to a second connection end of one of the through circuit lines.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: September 10, 2024
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yin-Chen Lin, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20240243097
    Abstract: A power module package structure includes a first substrate and a power component. The first substrate includes at least one conductive layer on a surface thereof. The power component includes a first chip and a first spacer. The first chip has at least one electrode. The first spacer in a heat dissipation space between the first substrate and the first chip includes an insulating heat dissipation layer in the heat dissipation space and multiple vertical conductive connectors, each of the vertical conductive connectors penetrates the insulating heat dissipation layer. The insulating heat dissipation layer surrounds the vertical conductive connectors and electrically isolates the vertical conductive connectors. The vertical conductive connector includes two opposite ends, one end electrically connected to the conductive layer, and the other end electrically connected to the electrode to form a conductive path and a heat dissipation path between the first chip and the first substrate.
    Type: Application
    Filed: January 18, 2024
    Publication date: July 18, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Ming Peng, I-Hung Chiang, Chun-Kai Liu, Po-Kai Chiu, Hsin-Han Lin, Kuo-Shu Kao
  • Publication number: 20240112969
    Abstract: An in-mold electronic (IME) device includes a curved substrate, a first conductive layer, a dielectric layer, a gap compensation layer, and a second conductive layer. The curved substrate has a first surface. The first conductive layer is disposed on the first surface. The dielectric layer is disposed on the first conductive layer and has a first thickness. The gap compensation layer is disposed on the first surface and connected to the dielectric layer. The gap compensation layer has a second thickness. The second conductive layer is disposed on the gap compensation layer and electrically connected to the gap compensation layer. A curvature radius of the curved substrate is c, a ratio of the second thickness to the first thickness is r, and c and r satisfy a relationship: r=1.5?0.02c±15%.
    Type: Application
    Filed: July 28, 2023
    Publication date: April 4, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Ming Peng, Hsiao-Fen Wei, Chih-Chia Chang
  • Patent number: 11937541
    Abstract: A grass cutting head includes a spool for winding a grass cutting line, a head housing for accommodating the spool, a first guiding structure disposed at least partially in the head housing, and a second guiding structure formed on the spool. The first guiding structure guides the grass cutting line through the head housing when threading the grass cutting line. The second guiding structure guides the grass cutting line to move and be wound around the spool by relative motion created between the spool and the head housing. The head housing includes a first housing and a second housing. The first guiding structure is disposed at least partially in the first housing. The spool is disposed between the first housing and the second housing. The first housing or the second housing is provided with an outer threading hole for allowing the grass cutting line to pass in or out.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: March 26, 2024
    Assignee: Nanjing Chervon Industry Co., Ltd.
    Inventors: Ming Peng, Jianpeng Guo, Dehong Ren
  • Publication number: 20240021727
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 18, 2024
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Publication number: 20240014118
    Abstract: In a flip chip package, lines, an identification line and a dummy line are provided on a first surface of a light-transmissive carrier, and a supportive layer is disposed on a second surface of the light-transmissive carrier. Bumps and an identification bump of a chip are bonded to the lines and the identification line, respectively. Shadows of the dummy line, the identification line and the identification bump which are projected on the second surface are visible from an opening of the supportive layer. The shadows can be inspected through the opening so as to know whether the bumps are bonded to the lines correctly.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 11, 2024
    Inventors: Chun-Te Lee, Chih-Ming Peng, Pi-Yu Peng, Hui-Yu Huang, Yin-Chen Lin
  • Publication number: 20230380053
    Abstract: A flip-chip bonding structure includes a chip and a circuit board, the chip is bonded to the circuit board by bumps. The circuit board includes a light-transmissive substrate, a first circuit group, a second circuit group, a boundary circuit and an identifying member. The boundary circuit is located between the first and second circuit groups and projects a boundary circuit shadow on light-transmissive substrate. The boundary circuit shadow can be recognized according to the identifying member and is provided to identify the boundary between the first and second circuit groups or identify the position of leads with the smallest pitch.
    Type: Application
    Filed: April 13, 2023
    Publication date: November 23, 2023
    Inventors: Chun-Te Lee, Chih-Ming Peng, Pi-Yu Peng, Hui-Yu Huang
  • Patent number: 11804547
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Patent number: 11792923
    Abstract: A storage device of the present invention is provided to store flexible circuit packages, each of the flexible circuit packages includes an electronic component and two circuit portions warped at both sides of the electronic component, respectively. The storage device includes a first carrier and a second carrier. The first carrier includes first accommodation elements provided for placement of the flexible circuit packages, and the second carrier includes a first press portion and a second press portion. As the second carrier is placed on the first carrier, the first and second press portions are provided to press the two circuit portions warped upwardly toward the second carrier so as to reduce the warpage of the two circuit portions.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: October 17, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Shih-Chieh Chang, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20230199961
    Abstract: An electronic apparatus including a compression molding board and a connection pad is provided. The compression molding board has a device bonding area and a bending area formed by compression molding. The device bonding area is different from the bending area. The connection pad is disposed on the device bonding area of the compression molding board.
    Type: Application
    Filed: March 24, 2022
    Publication date: June 22, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Lin Hsu, Kuan-Chu Wu, Ting-Yu Ke, Min-Hsiung Liang, Yu-Ming Peng
  • Patent number: 11682847
    Abstract: An antenna array device and an antenna unit thereof are provided. The antenna unit includes an antenna structure and a molding support. The antenna structure includes a substrate and a plurality of patches that are formed on the substrate. The substrate has a plurality of channel holes penetrating there-through. The molding support is integrally formed on the substrate as a single one-piece structure. The molding support has a first stand, a second stand, and a plurality of connection portions that are formed in the channel holes to connect the first stand and the second stand. The first stand and the second stand are formed on two sides of the substrate, respectively.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: June 20, 2023
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Shih-Hong Chen, Chien-Ming Peng, Chao-Chun Lin, Yu-Fu Kuo
  • Publication number: 20230154877
    Abstract: An electronic device includes a substrate, an electronic component, a first interposing layer and a second interposing layer. The substrate is non-planar and the substrate includes a first substrate pad and a second substrate pad. The electronic component includes a first component pad and a second component pad corresponding to the first substrate pad and the second substrate pad respectively. When the first component pad contacts the first substrate pad, a height difference exists between the second component pad and the second substrate pad. The first interposing layer connects between the first component pad and the first substrate pad. The second interposing layer connects between the second component pad and the second substrate pad. A thickness difference between the first interposing layer and the second interposing layer is 0.5 to 1 time the height difference.
    Type: Application
    Filed: March 24, 2022
    Publication date: May 18, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Ming Peng, Chien-Chou Tseng, Chih-Chia Chang, Kuan-Chu Wu, Yu-Lin Hsu
  • Patent number: 11640105
    Abstract: A projector includes a light source module, a light valve, and a projection lens. The light source module is adapted to provide an illumination light beam and includes a base having first and second side surfaces, first and second color light-emitting units respectively disposed on the first and second side surfaces, and first and second heat dissipation structures respectively connected to the first and second color light-emitting units. The first and second heat dissipation structures are separated from each other and define an accommodation space together. The light valve is located on a transmission path of the illumination light beam and adapted to convert the illumination light beam into an image light beam. The projection lens is located on a transmission path of the image light beam and adapted to project the image light beam.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: May 2, 2023
    Assignee: Coretronic Corporation
    Inventors: Chien-Ming Peng, Yen-Po Chang, Mao-Min Fu, Wei-Min Chien
  • Patent number: 11638367
    Abstract: An electronic device includes a substrate, at least one electronic element and a heat dissipating electromagnetic shielding structure. The heat dissipating electromagnetic shielding structure is disposed on the substrate and covers the at least one electronic element, wherein the heat dissipating electromagnetic shielding structure includes a shielding frame and a heatsink. The shielding frame includes a plurality of spring members. The spring members are bent toward the substrate and partially abut against the heatsink. When the heatsink and the shielding frame are correspondingly arranged, a shielding space is defined, the electronic element is disposed in the shielding space, and a heat generated by the at least one electronic element is conducted out of the shielding space via the heatsink.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 25, 2023
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Yan-Da Chen, Chien-Ming Peng, Yu-Jen Liu, Chih-Chuan Lin, Chi-Te Lin
  • Patent number: 11602047
    Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: March 7, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yin-Chen Lin, Ming-Hsiao Ke, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee