Patents by Inventor MING RAN LIU
MING RAN LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250005323Abstract: A method, system, and computer program product that is configured to: receive at least one workload of a mixed addressing mode application; classify the at least one workload with artificial intelligence (AI) including a support vector machine (SVM) algorithm; match at least one agent to the at least one workload based on a workload class and tuning policies; execute workload polices of the at least one workload based on the workload class and the tuning policies; evaluate a transaction per second (TPS) and response time of the at least one workload; calculate a reward of the at least one workload; and train a plurality of models based on historical data corresponding to the evaluated TPS, the evaluated response time, and the calculated reward.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Inventors: NAIJIE LI, Peng Hui Jiang, Bao Zhang, Jing Lu, Ming Ran Liu, Yuan Zhai, Dong Hui Liu
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Patent number: 11947993Abstract: A computer-implemented method includes creating a first file control block in a primary runtime environment with a first addressing mode and a second file control block in a secondary runtime environment with a second addressing mode, where both the first file control block and the second file control block describe a status of a first file of a caller program in the primary runtime environment. The parameters of the first file of the caller program in the primary runtime environment are passed to a target callee program in the secondary runtime environment. An anchor is added in the first file control block as a link to the second file control block. The first file control block are the second file control block synchronized with updates to the first file in the primary runtime environment and the passed parameters of the first file in the secondary runtime environment.Type: GrantFiled: June 22, 2021Date of Patent: April 2, 2024Assignee: International Business Machines CorporationInventors: Ming Ran Liu, Jing Lu, Naijie Li, Xiao Yan Tang, Yuan Zhai, Kershaw S. Mehta
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Publication number: 20230267005Abstract: A thread management process where a storage area template is generated for a plurality of threads that are to be created by a process in a computing system, the storage area template comprising at least one module template for at least one library that is to be loaded by the process. In the computing system, a plurality of storage areas is allocated for the plurality of threads based on the storage area template, respectively. The plurality of threads are managed based on the plurality of storage areas, respectively. All threads and libraries may be managed in a uniform way according to the storage area template. Therefore, thread management may be simplified and then may lead to reduced costs in the storage and time resources.Type: ApplicationFiled: February 22, 2022Publication date: August 24, 2023Inventors: NAIJIE LI, Bao Zhang, Ming Ran Liu, Yuan Zhai, Jia Yu, Peng Hui Jiang, Guang Han Sui
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Publication number: 20230185903Abstract: A first memory page in a memory of the computer is allocated as a first stack to buffer meta data for function calls in the program. A memory protection key for the first memory page is generated. A second memory page in the memory is allocated as a second stack to buffer user data for function calls in the program.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Inventors: Naijie Li, Jing Lu, Ming Ran Liu, Xiao Yan Tang, Yuan Zhai, Guang Han Sui
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Publication number: 20230136606Abstract: Global variables are shared between programs associated with different addressing modes. A first program of an application records an allocated address to a global variable in a global variable sharing area (GVSA). The first program is associated with a first addressing mode. The first program specifies the global variable to be shared across different addressing modes. An address of the GVSA is passed to a second program of the application that is loaded after the first program has been loaded. The second program is associated with a second addressing mode different from the first addressing mode. The second program also specifies the global variable in the second program to be shared across different addressing modes. The second program retrieves the allocated address to the global variable from the GVSA based on the address of the GVSA. The second program accesses the global variable based on the retrieved allocated address.Type: ApplicationFiled: November 3, 2021Publication date: May 4, 2023Inventors: Xiao Yan Tang, Naijie Li, Jing Lu, Ming Ran Liu, Yuan Zhai, Kershaw S. Mehta
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Patent number: 11556356Abstract: A call to an external interface to execute a target callee program associated with a first addressing mode in a secondary runtime environment (RTE) is received from a caller program associated with a second addressing mode running in a primary RTE. An address of a share area (SA) storing existing dynamic link object information in the primary RTE in storage is passed to the secondary RTE. The SA is accessible by both the caller program and the target callee program. In response to a request to load a dynamic link object by an initiating program during execution of the target callee program in the secondary RTE, an entry address of the dynamic link object is retrieved in the SA. The dynamic link object is loaded based on the retrieved entry address of the dynamic link object.Type: GrantFiled: September 23, 2021Date of Patent: January 17, 2023Assignee: International Business Machines CorporationInventors: Naijie Li, Jing Lu, Xiao Yan Tang, Ming Ran Liu, Yuan Zhai, Kershaw S. Mehta
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Publication number: 20220405118Abstract: Aspects of the invention include creating a first file control block in a primary runtime environment with a first addressing mode and a second file control block in a second runtime environment with a second addressing mode, where both the first file control block and the second file control block describe a status of a first file of a caller program in the primary runtime environment. The parameters of the first file of the caller program in the primary runtime environment are passed to a target callee program in the secondary runtime environment. An anchor is added in the first file control block as a link to the second file control block. The first file control block are the second file control block synchronized with updates to the first file in the primary runtime environment and the passed parameters of the first file in the secondary runtime environment.Type: ApplicationFiled: June 22, 2021Publication date: December 22, 2022Inventors: Ming Ran Liu, Jing Lu, NAIJIE LI, Xiao Yan Tang, Yuan Zhai, Kershaw S. Mehta
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Publication number: 20220374233Abstract: In an approach for improving data access performance in memory, a processor monitors each data access to a data element in the memory from an application, wherein the application has a plurality of functions. A processor records, during runtime, each data access into a monitoring element table, wherein the record for each data access includes an identity, a start address, an end address, and a memory page number. A processor clusters recorded data accesses for each function based on a distance between data elements accessed in sequence. A processor allocates, based on the data element clustering result, the data elements in a same cluster into a same memory unit in the memory.Type: ApplicationFiled: May 24, 2021Publication date: November 24, 2022Inventors: Ming Ran Liu, Xiao Yan Tang, Bao Zhang, Jing Lu, Dong Hui Liu, Peng Hui Jiang, Yong Yin, Jia Yu
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Patent number: 11500653Abstract: Techniques for signal handling between programs associated with different addressing modes in a computer system are described herein. An aspect includes, based on a signal occurring during execution of a first program in a first runtime environment, wherein the first program and the first runtime environment are associated with a first addressing mode, invoking a first signal exit routine associated with the first addressing mode. Another aspect includes allocating a signal information area (SIA) by the first signal exit routine. Another aspect includes calling a second signal exit routine associated with a second addressing mode that is different from the first addressing mode with an address of the SIA. Another aspect includes allocating a mirror SIA by the second signal exit routine. Another aspect includes handling the signal, and resuming execution based on the handling of the signal.Type: GrantFiled: February 5, 2020Date of Patent: November 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ming Ran Liu, Bao Zhang, Naijie Li, Jing Lu, Xiao Yan Tang, Kershaw S. Mehta
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Patent number: 11442739Abstract: Embodiments of the present disclosure relate to a method, system, and computer program product for exception handling. In some embodiments, a method is disclosed. According to the method, in response to an application throwing an exception, a target stack frame for handling the exception is detected from a call stack of the application. The call stack comprises a plurality of stack frames. One of the plurality of stack frames corresponds to a function called by the application and supports either a one-phase exception handling mechanism or a two-phase exception handling mechanism. In response to the target stack frame being detected from the call stack, the target stack frame is caused to handle the exception. In other embodiments, a system and a computer program product are disclosed.Type: GrantFiled: September 16, 2019Date of Patent: September 13, 2022Assignee: International Business Machines CarporationInventors: Ming Ran Liu, Bao Zhang, Naijie Li, Yuan Zhai, Sean Douglas Perry
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Patent number: 11294695Abstract: A computer-implemented method for termination of programs associated with different addressing modes includes receiving a call to an external interface to execute a target callee program from a caller program executing in a primary runtime environment. The external interface allocates an interoperability term area (ITA) in a primary runtime environment. The ITA is accessible by the primary runtime environment and a secondary runtime environment. The external interface executes the target callee program in the secondary runtime environment. The target callee program sets a termination reason parameter in the ITA. In response to the target callee program setting the termination reason parameter, a termination action in the primary runtime environment is performed. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: May 28, 2020Date of Patent: April 5, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiao Yan Tang, Naijie Li, Jing Lu, Ming Ran Liu, Kershaw S. Mehta
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Patent number: 11288105Abstract: Provided is a method for preventing deadlocks between competing threads. The method includes receiving a lock request from a first thread and, in response, identifying a potential deadlock with a second thread. In response, the method includes determining whether to deny the lock request, which includes: determining whether a first duration for which the first thread will hold the lock to complete its job is longer than a second duration for which the second thread will hold the lock to complete its job; determining whether the second thread will start to use the lock soon relative to the first duration; and determining whether both the first and second threads will complete their respective jobs within a time limit if the lock is denied to the first thread while the second thread completes its job. The method further includes denying the request for the requested lock from the first thread.Type: GrantFiled: July 27, 2020Date of Patent: March 29, 2022Assignee: International Business Machines CorporationInventors: Jing Lu, Bao Zhang, Ming Ran Liu, Tie Liu, Xiao Yan Tang, Xiang Zu
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Publication number: 20220027213Abstract: Provided is a method for preventing deadlocks between competing threads. The method includes receiving a lock request from a first thread and, in response, identifying a potential deadlock with a second thread. In response, the method includes determining whether to deny the lock request, which includes: determining whether a first duration for which the first thread will hold the lock to complete its job is longer than a second duration for which the second thread will hold the lock to complete its job; determining whether the second thread will start to use the lock soon relative to the first duration; and determining whether both the first and second threads will complete their respective jobs within a time limit if the lock is denied to the first thread while the second thread completes its job. The method further includes denying the request for the requested lock from the first thread.Type: ApplicationFiled: July 27, 2020Publication date: January 27, 2022Inventors: Jing Lu, Bao Zhang, Ming Ran Liu, Tie Liu, Xiao Yan Tang, Xiang Zu
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Publication number: 20210373917Abstract: A computer-implemented method for termination of programs associated with different addressing modes includes receiving a call to an external interface to execute a target callee program from a caller program executing in a primary runtime environment. The external interface allocates an interoperability term area (ITA) in a primary runtime environment. The ITA is accessible by the primary runtime environment and a secondary runtime environment. The external interface executes the target callee program in the secondary runtime environment. The target callee program sets a termination reason parameter in the ITA. In response to the target callee program setting the termination reason parameter, a termination action in the primary runtime environment is performed. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Inventors: Xiao Yan Tang, Naijie Li, Jing Lu, Ming Ran Liu, Kershaw S. Mehta
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Publication number: 20210240495Abstract: Techniques for signal handling between programs associated with different addressing modes in a computer system are described herein. An aspect includes, based on a signal occurring during execution of a first program in a first runtime environment, wherein the first program and the first runtime environment are associated with a first addressing mode, invoking a first signal exit routine associated with the first addressing mode. Another aspect includes allocating a signal information area (SIA) by the first signal exit routine. Another aspect includes calling a second signal exit routine associated with a second addressing mode that is different from the first addressing mode with an address of the SIA. Another aspect includes allocating a mirror SIA by the second signal exit routine. Another aspect includes handling the signal, and resuming execution based on the handling of the signal.Type: ApplicationFiled: February 5, 2020Publication date: August 5, 2021Inventors: Ming Ran Liu, Bao Zhang, NAIJIE LI, Jing Lu, Xiao Yan Tang, Kershaw S. Mehta
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Publication number: 20210081208Abstract: Embodiments of the present disclosure relate to a method, system, and computer program product for exception handling. In some embodiments, a method is disclosed. According to the method, in response to an application throwing an exception, a target stack frame for handling the exception is detected from a call stack of the application. The call stack comprises a plurality of stack frames. One of the plurality of stack frames corresponds to a function called by the application and supports either a one-phase exception handling mechanism or a two-phase exception handling mechanism. In response to the target stack frame being detected from the call stack, the target stack frame is caused to handle the exception. In other embodiments, a system and a computer program product are disclosed.Type: ApplicationFiled: September 16, 2019Publication date: March 18, 2021Inventors: Ming Ran Liu, Bao Zhang, NAIJIE LI, Yuan Zhai, Sean Douglas Perry
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Patent number: 10694034Abstract: Provided are systems, methods, and media for verifying a commission-based relationship in a communication system. An example method includes generating authorization information by an authorizer that is to be transmitted to a caller and forwarded by the caller to a callee upon a call being initiated between the caller and the callee, in which the authorization information includes at least authorizer identity information, callee identity information, and a caller public key. The method includes signing the authorization information with a private key of the authorizer and transmitting the signed authorization information to the caller. The caller is configured to generate a digital signature via a private key of the caller and transmit the digital signature and the signed authorization information to the callee. The callee is configured to verify the identity of authorizer, caller and callee and event information based on the authorization information.Type: GrantFiled: December 12, 2018Date of Patent: June 23, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiao Yan Tang, Tao Liu, Jing Lu, Ming Ran Liu, Xiao Ling Chen
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Publication number: 20200195778Abstract: Provided are systems, methods, and media for verifying a commission-based relationship in a communication system. An example method includes generating authorization information by an authorizer that is to be transmitted to a caller and forwarded by the caller to a callee upon a call being initiated between the caller and the callee, in which the authorization information includes at least authorizer identity information, callee identity information, and a caller public key. The method includes signing the authorization information with a private key of the authorizer and transmitting the signed authorization information to the caller. The caller is configured to generate a digital signature via a private key of the caller and transmit the digital signature and the signed authorization information to the callee. The callee is configured to verify the identity of authorizer, caller and callee and event information based on the authorization information.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Xiao Yan Tang, Tao Liu, Jing Lu, Ming Ran Liu, Xiao Ling Chen
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Patent number: 10613842Abstract: A computer-implemented method includes receiving an initial control flow graph (CFG) describing a project, where the project includes one or more programs. The initial CFG includes a plurality of graph nodes and a plurality of edges connecting the plurality of graph nodes to one another. Based on first profiling data, a first set of one or more graph nodes of the plurality of graph nodes of the initial CFG is selected as a first set of main nodes. The first profiling data describes a first execution history of the project. The initial CFG is simplified by generating a first final CFG, which includes the first set of main nodes and excludes one or more remaining nodes of the initial CFG that are not in the first set of main nodes.Type: GrantFiled: April 30, 2018Date of Patent: April 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bao Zhang, Naijie Li, Ming Ran Liu, Yuan Zhai
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Publication number: 20190332364Abstract: A computer-implemented method includes receiving an initial control flow graph (CFG) describing a project, where the project includes one or more programs. The initial CFG includes a plurality of graph nodes and a plurality of edges connecting the plurality of graph nodes to one another. Based on first profiling data, a first set of one or more graph nodes of the plurality of graph nodes of the initial CFG is selected as a first set of main nodes. The first profiling data describes a first execution history of the project. The initial CFG is simplified by generating a first final CFG, which includes the first set of main nodes and excludes one or more remaining nodes of the initial CFG that are not in the first set of main nodes.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Inventors: BAO ZHANG, NAIJIE LI, MING RAN LIU, YUAN ZHAI