Patents by Inventor Ming-Shan Lo
Ming-Shan Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10692981Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a first gate structure, a second gate structure, an oxide layer and a nitride layer. The first gate structure and the second gate structure are disposed on a substrate. The oxide layer covers the first gate structure. The nitride layer is disposed on the substrate and covers the oxide and the second gate structure. The refraction index of a portion of the nitride layer adjacent to an interface between the nitride layer and each of the first gate structure and the second gate structure is about 5% to 10% less than the refraction index of the remaining portion of the nitride layer.Type: GrantFiled: February 27, 2019Date of Patent: June 23, 2020Assignee: eMemory Technology Inc.Inventors: Yen-Ting Chen, Ming-Shan Lo
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Patent number: 10664239Abstract: A method of programming a nonvolatile memory cell is provided according to an embodiment of the invention. The nonvolatile memory cell includes a substrate; and a select transistor, a following gate transistor, and an anti-fuse transistor comprising a first gate oxide layer, disposed on the substrate and coupled in series with each other. The programming method includes applying to said nonvolatile memory cell a variable DC voltage source comprising at least one high voltage part for forming a trapping path within the first gate oxide layer and at least one low voltage part for crystallizing the trapping path into a silicon filament.Type: GrantFiled: September 10, 2018Date of Patent: May 26, 2020Assignee: eMemory Technology Inc.Inventors: Kuan-Hsun Chen, Chun-Hung Lu, Ming-Shan Lo
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Publication number: 20190326304Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a first gate structure, a second gate structure, an oxide layer and a nitride layer. The first gate structure and the second gate structure are disposed on a substrate. The oxide layer covers the first gate structure. The nitride layer is disposed on the substrate and covers the oxide and the second gate structure. The refraction index of a portion of the nitride layer adjacent to an interface between the nitride layer and each of the first gate structure and the second gate structure is about 5% to 10% less than the refraction index of the remaining portion of the nitride layer.Type: ApplicationFiled: February 27, 2019Publication date: October 24, 2019Applicant: eMemory Technology Inc.Inventors: Yen-Ting Chen, Ming-Shan Lo
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Patent number: 10283511Abstract: A non-volatile memory including memory cells is provided. Each of the memory cells includes a substrate, a floating gate structure, a select gate structure, and a first doped region. The floating gate structure is disposed on the substrate. The select gate structure is disposed on the substrate and located at one side of the floating gate structure. The first doped region is disposed in the substrate at another side of the floating gate structure. The first doped regions between two adjacent memory cells are adjacent to one another and separated from one another.Type: GrantFiled: March 22, 2017Date of Patent: May 7, 2019Assignee: eMemory Technology Inc.Inventors: Yi-Hung Li, Ming-Shan Lo, Cheng-Da Huang
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Publication number: 20190080778Abstract: A method of programming a nonvolatile memory cell is provided according to an embodiment of the invention. The nonvolatile memory cell includes a substrate; and a select transistor, a following gate transistor, and an anti-fuse transistor comprising a first gate oxide layer, disposed on the substrate and coupled in series with each other. The programming method includes applying to said nonvolatile memory cell a variable DC voltage source comprising at least one high voltage part for forming a trapping path within the first gate oxide layer and at least one low voltage part for crystallizing the trapping path into a silicon filament.Type: ApplicationFiled: September 10, 2018Publication date: March 14, 2019Applicant: eMemory Technology Inc.Inventors: Kuan-Hsun Chen, Chun-Hung Lu, Ming-Shan Lo
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Patent number: 10083757Abstract: A single-poly NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first LDD region merged with the source doping region, a commonly-shared doping region, and a second LDD region merged with the commonly-shared doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region. A drain-side extension modified region is disposed under the spacer and in proximity to the drain doping region.Type: GrantFiled: October 14, 2016Date of Patent: September 25, 2018Assignee: eMemory Technology Inc.Inventors: Kuan-Hsun Chen, Ming-Shan Lo, Ting-Ting Su
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Publication number: 20180102376Abstract: A non-volatile memory including memory cells is provided. Each of the memory cells includes a substrate, a floating gate structure, a select gate structure, and a first doped region. The floating gate structure is disposed on the substrate. The select gate structure is disposed on the substrate and located at one side of the floating gate structure. The first doped region is disposed in the substrate at another side of the floating gate structure. The first doped regions between two adjacent memory cells are adjacent to one another and separated from one another.Type: ApplicationFiled: March 22, 2017Publication date: April 12, 2018Applicant: eMemory Technology Inc.Inventors: Yi-Hung Li, Ming-Shan Lo, Cheng-Da Huang
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Publication number: 20180019250Abstract: A UV-erasable memory device with a UV transmitting window is disclosed. The UV-erasable memory device includes a substrate, two serially connected PMOS transistors on the substrate; an interlayer dielectric (ILD) layer covering the two PMOS transistors, a first intermetal dielectric (IMD) layer on the ILD layer, an intermediate layer on the first IMD layer, a UV transmitting window in the intermediate layer, and a second intermetal dielectric (IMD) layer on the first IMD layer and in the UV transmitting window.Type: ApplicationFiled: June 22, 2017Publication date: January 18, 2018Inventors: Ting-Ting Su, Kuan-Hsun Chen, Ming-Shan Lo
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Patent number: 9640259Abstract: A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.Type: GrantFiled: November 20, 2015Date of Patent: May 2, 2017Assignee: eMemory Technology Inc.Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
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Publication number: 20170110467Abstract: A single-poly NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first LDD region merged with the source doping region, a commonly-shared doping region, and a second LDD region merged with the commonly-shared doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region. A drain-side extension modified region is disposed under the spacer and in proximity to the drain doping region.Type: ApplicationFiled: October 14, 2016Publication date: April 20, 2017Inventors: Kuan-Hsun Chen, Ming-Shan Lo, Ting-Ting Su
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Publication number: 20160079251Abstract: A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.Type: ApplicationFiled: November 20, 2015Publication date: March 17, 2016Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
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Patent number: 9236453Abstract: According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.Type: GrantFiled: March 30, 2014Date of Patent: January 12, 2016Assignee: eMemory Technology Inc.Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
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Publication number: 20150091073Abstract: According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.Type: ApplicationFiled: March 30, 2014Publication date: April 2, 2015Applicant: EMEMORY TECHNOLOGY INC.Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang