Patents by Inventor Ming-Shan SHIEH
Ming-Shan SHIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10700176Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.Type: GrantFiled: October 24, 2019Date of Patent: June 30, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
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Patent number: 10672769Abstract: A method includes forming a transistor over a substrate, wherein the transistor includes a source, a drain over the source, a semiconductor channel between the source and the drain, and a gate surrounding the semiconductor channel. A silicide layer is formed over the drain of the transistor. A capping layer is formed over the silicide layer. Portions of the capping layer and the silicide layer are removed to define a drain pad over the drain of the transistor.Type: GrantFiled: May 25, 2018Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Wai-Yi Lien, Chih-Hao Wang
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Publication number: 20200075742Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.Type: ApplicationFiled: October 24, 2019Publication date: March 5, 2020Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
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Patent number: 10483367Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.Type: GrantFiled: January 16, 2018Date of Patent: November 19, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
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Publication number: 20180277538Abstract: A method includes forming a transistor over a substrate, wherein the transistor includes a source, a drain over the source, a semiconductor channel between the source and the drain, and a gate surrounding the semiconductor channel. A silicide layer is formed over the drain of the transistor. A capping layer is formed over the silicide layer. Portions of the capping layer and the silicide layer are removed to define a drain pad over the drain of the transistor.Type: ApplicationFiled: May 25, 2018Publication date: September 27, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao CHANG, Ming-Shan SHIEH, Cheng-Long CHEN, Wai-Yi LIEN, Chih-Hao WANG
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Patent number: 9985026Abstract: A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises multiple conductive layers.Type: GrantFiled: August 15, 2014Date of Patent: May 29, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Wai-Yi Lien, Chih-Hao Wang
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Publication number: 20180138282Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.Type: ApplicationFiled: January 16, 2018Publication date: May 17, 2018Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
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Patent number: 9899489Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.Type: GrantFiled: March 17, 2015Date of Patent: February 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
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Patent number: 9893159Abstract: A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises a single implanted silicide layer or a multiple conductive layers with the implanted silicide layer.Type: GrantFiled: December 24, 2014Date of Patent: February 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Chang, Ming-Shan Shieh, Wai-Yi Lien
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Patent number: 9881922Abstract: Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.Type: GrantFiled: August 1, 2016Date of Patent: January 30, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Lin Chen, Shih-Cheng Chen, Ming-Shan Shieh, Chin-Chi Wang, Wai-Yi Lien, Chih-Hao Wang
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Publication number: 20160343713Abstract: Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.Type: ApplicationFiled: August 1, 2016Publication date: November 24, 2016Inventors: Hong-Lin Chen, Shih-Cheng Chen, Ming-Shan Shieh, Chin-Chi Wang, Wai-Yi Lien, Chih-Hao Wang
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Patent number: 9431517Abstract: Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.Type: GrantFiled: January 9, 2015Date of Patent: August 30, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Lin Chen, Shih-Cheng Chen, Ming-Shan Shieh, Chin-Chi Wang, Wai-Yi Lien, Chih-Hao Wang
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Publication number: 20160240626Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.Type: ApplicationFiled: March 17, 2015Publication date: August 18, 2016Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
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Publication number: 20160240623Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.Type: ApplicationFiled: February 13, 2015Publication date: August 18, 2016Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
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Patent number: 9406780Abstract: Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.Type: GrantFiled: January 9, 2015Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Lin Chen, Shih-Cheng Chen, Ming-Shan Shieh, Chin-Chi Wang, Wai-Yi Lien, Chih-Hao Wang
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Publication number: 20160149019Abstract: Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.Type: ApplicationFiled: January 9, 2015Publication date: May 26, 2016Inventors: Hong-Lin Chen, Shih-Cheng Chen, Ming-Shan Shieh, Chin-Chi Wang, Wai-Yi Lien, Chih-Hao Wang
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Publication number: 20160049397Abstract: A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises multiple conductive layers.Type: ApplicationFiled: August 15, 2014Publication date: February 18, 2016Inventors: Chia-Hao CHANG, Ming-Shan SHIEH, Cheng-Long CHEN, Wai-Yi LIEN, Chih-Hao WANG
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Publication number: 20160049480Abstract: A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises a single implanted silicide layer or a multiple conductive layers with the implanted silicide layer.Type: ApplicationFiled: December 24, 2014Publication date: February 18, 2016Inventors: Chia-Hao Chang, Ming-Shan Shieh, Wai-Yi Lien