Patents by Inventor Ming Shen

Ming Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140573
    Abstract: A method of manufacturing pre-molded lead frame for packaging is disclosed. A first patterned aluminum metal layer is formed on a temporary carrier. A displacement reaction procedure is performed, in which at least part of the first patterned aluminum metal layer is replaced by copper metal so as to form a first copper metal wiring layer. A first molding compound is formed around the first copper metal wiring layer. The temporary carrier is removed.
    Type: Application
    Filed: December 28, 2023
    Publication date: May 1, 2025
    Applicant: PANJIT INTERNATIONAL INC.
    Inventors: Chung Hsiung HO, Wei-Ming HUNG, Shun Chi SHEN
  • Publication number: 20250138404
    Abstract: A projector includes a light source module, a light valve, and a projecting lens. The light source module includes a light-emitting element, a light diffusion assembly, a first structural component, and a first temperature-sensing element. The light-emitting element is adapted to emit an illumination light beam. The light diffusion assembly is adapted to diffuse the illumination light beam. The light diffusion assembly has a front end and a rear end opposite to each other, the front end of the light diffusion assembly faces the light-emitting element, and the rear end of the light diffusion assembly faces the first structural component. The first temperature-sensing element is disposed on the first structural component and corresponds to the light diffusion assembly. The light valve is adapted to convert the illumination light beam from the light source module into an image light beam. The projecting lens is adapted to project the image light beam.
    Type: Application
    Filed: October 15, 2024
    Publication date: May 1, 2025
    Applicant: Qisda Corporation
    Inventors: Hsin-Liang Chen, Chun Ming Shen
  • Patent number: 12289893
    Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Qing Shi, Bo-Feng Young, Yu-Chuan Shih, Sai-Hooi Yeong, Blanka Magyari-Kope, Ying-Chih Chen, Tzer-Min Shen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20250128214
    Abstract: A gas mixing system for semiconductor fabrication includes a mixing block. The mixing block defines a gas mixing chamber, a first gas channel fluidly coupled to the gas mixing chamber at a first exit location, and a second gas channel fluidly coupled to the gas mixing chamber at a second exit location, wherein the first exit location is diametrically opposite the second exit location relative to the gas mixing chamber and the second gas channel has a bend of 90 degrees or less between an entrance of the second gas channel and the second exit location.
    Type: Application
    Filed: December 30, 2024
    Publication date: April 24, 2025
    Inventors: Ming Shing LIN, Chin Shen HSIEH
  • Publication number: 20250129912
    Abstract: A projector device including a device body, a first heat dissipation component, a second heat dissipation component, a third heat dissipation component, and a heat dissipation fan. The device body includes a light emitting element, a wavelength conversion element, a light valve, and a projection lens. The first heat dissipation component, the second heat dissipation component, and the third heat dissipation component are connected to the light emitting element, the light valve, and the wavelength conversion element. The heat dissipation fan has an air outlet surface and is adapted to provide a heat dissipation airflow. The air outlet surface faces at least one of the first heat dissipation component, the second heat dissipation component, and the third heat dissipation component. The first heat dissipation component, the second heat dissipation component and the third heat dissipation component are all located on at least one flow path of the heat dissipation airflow.
    Type: Application
    Filed: October 1, 2024
    Publication date: April 24, 2025
    Applicant: Qisda Corporation
    Inventors: Hsin-Liang Chen, Chun Ming Shen, Chien Yu Shih
  • Patent number: 12276809
    Abstract: Disclosed are a super-resolution imaging system (1, 41, 51), a super-resolution imaging method, a biological sample identification system (4, 61) and method, a nucleic acid sequencing imaging system (5) and method, and a nucleic acid identification system (6) and method. The super-resolution imaging system (1, 41, 51) includes an illumination system (A) and an imaging system (B). The illumination system (A) outputs excitation light to irradiate a biological sample to generate excited light, and the imaging system (B) collects and records the excited light to generate an excited light image. The illumination system (A) includes an excitation light source (10, 10a) and a structured light generation and modulation device (11, 11a). The excitation light source (10, 10a) outputs the excitation light, and the structured light generation and modulation device (11, 11a) modulates the excitation light into structured light to irradiate the biological sample to generate the excited light.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: April 15, 2025
    Assignee: BGI SHENZHEN
    Inventors: Jielei Ni, Ming Ni, Fan Zhou, Zeyu Su, Ke Ji, Dong Wei, Mengzhe Shen, Yuanqing Liang, Mei Li, Xun Xu
  • Publication number: 20250118615
    Abstract: A package structure includes a package substrate, an interposer module, a package lid, and a heat dissipation structure between the interposer module and the package lid, including a thermal interface material (TIM) layer, and a metal barrier layer between the TIM layer and at least one of the interposer module or the package lid, and configured to inhibit formation of an intermetallic compound (IMC) layer. A method of making the package structure includes forming a metal barrier layer comprising Cu (111) on at least one of an interposer module or a package lid, attaching the interposer module, forming a thermal interface material (TIM) layer over the interposer module, and attaching the package lid to the package substrate so that the interposer module, the TIM layer and the metal barrier layer are disposed between the package lid and the package substrate, and the metal barrier layer contacts the TIM layer.
    Type: Application
    Filed: February 26, 2024
    Publication date: April 10, 2025
    Inventors: Jui Shen Chang, Chen-Nan Chiu, Yao-Chun Chuang, Chang-Jung Hsueh, Ming-Da Cheng
  • Publication number: 20250118697
    Abstract: A package structure includes a package substrate, a chip on the package substrate, a package lid on the chip, and a structure between the chip and the package lid. The structure may include a thermal interface material (TIM) layer, and a metal layer between the TIM layer and at least one of the chip or the package lid and configured to inhibit formation of an intermetallic compound (IMC) layer. A method of making the package structure includes forming a metal layer including a high-texture structure on at least one of a chip or a package lid, attaching the chip to a package substrate, forming a thermal interface material (TIM) layer over the chip, and attaching the package lid to the package substrate over the chip so that the chip, the TIM layer and the metal layer are disposed between the package lid and the package substrate.
    Type: Application
    Filed: July 29, 2024
    Publication date: April 10, 2025
    Inventors: Jui Shen Chang, Chen-Nan Chiu, Yao-Chun Chuang, Chang-Jung Hsueh, Ming-Da Cheng
  • Publication number: 20250115473
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate with a first groove and a semiconductor device. The first groove has a first portion, a second portion, and a third portion, and the second portion is between the first portion and the third portion. The semiconductor device includes a membrane and is disposed on the second portion of the first groove. The semiconductor device has a first surface adjacent to the substrate and opposite to the membrane. The membrane is exposed by the first surface.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Liang HSIAO, Lu-Ming LAI, Ching-Han HUANG, Chia-Hung SHEN
  • Patent number: 12269952
    Abstract: The present invention discloses a fully bio-based, highly filled lignin-rubber masterbatch, a method for preparing same, and use thereof. The lignin-rubber masterbatch is prepared by a method comprising: (1) reacting a lignin, acetic acid, and oleic acid in the presence of a catalyst to give a modified lignin; and (2) blending the modified lignin and a rubber, and granulating to give the lignin-rubber masterbatch. The highly filled lignin-rubber masterbatch prepared by the present invention can replace the conventional reinforcing agent carbon black and provide a better reinforcing effect and higher mechanical properties for rubber materials. The present invention can also reduce the rubber content of the rubber composite materials while retaining the mechanical properties, thus featuring cost-efficiency.
    Type: Grant
    Filed: August 17, 2024
    Date of Patent: April 8, 2025
    Assignee: NANJING TECH UNIVERSITY
    Inventors: Chenjie Zhu, Haifeng Liu, Ming Li, Lei Ji, Zhiwei Chang, Yixin Feng, Zhuotao Tan, Tao Shen, Hanjie Ying
  • Patent number: 12266635
    Abstract: A semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Chia Yang, Shu-Shen Yeh, Po-Chen Lai, Ming-Chih Yew, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20250093593
    Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized to transmit and receive optical signals to and from an optical device. In embodiments the mirror structure receives optical signals from outside of an optical device and directs the optical signals through at least one mirror to an optical component of the optical device.
    Type: Application
    Filed: January 3, 2024
    Publication date: March 20, 2025
    Inventors: Wen-Chih Lin, Cheng-Yu Kuo, Yen-Hung Chen, Hsuan-Ting Kuo, Chia-Shen Cheng, Chao-Wei Li, Ching-Hua Hsieh, Wen-Chih Chiou, Ming-Fa Chen, Shang-Yun Hou
  • Publication number: 20250094682
    Abstract: Methods of designing integrated circuits incorporating an analog ECO flow are provided. An example method comprises receiving an initial design and performing an auto-marker process. The auto-marker process comprises performing a first auto-marker process to surround a first plurality of active cells of the design with first computer-aided design (CAD) layers corresponding to a first plurality of engineering change order (ECO) cells, performing an enhanced auto-marker process to cover irregular shapes of the design with second CAD layers corresponding to a second plurality of ECO cells, and performing a second auto-marker process to fill empty areas of the design with third CAD layers corresponding to a third plurality of ECO cells. The method further includes filling the design with the first plurality of ECO cells, the second plurality of ECO cells, and the third plurality of ECO cells.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Inventors: Ayushi Agrawal, Yu-Tao Yang, Ming-Cheng Syu, Wen-Shen Chou, Yung-Chow Peng
  • Publication number: 20250093612
    Abstract: A lens module including an integrated lens holder and a lens group is provided. The lens holder is composed of a fixed piece and a lens frame. The lens frame is connected to the fixed piece. The lens frame includes an accommodating cavity and a bearing surface located in a periphery of the accommodating cavity. The lens group is disposed in the accommodation cavity and is supported on the bearing surface.
    Type: Application
    Filed: August 16, 2024
    Publication date: March 20, 2025
    Applicant: Qisda Corporation
    Inventors: Hsin-Liang CHEN, Chun-Ming SHEN, Sheng-Wen HU
  • Patent number: 12254257
    Abstract: A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Cheng Syu, Po-Zeng Kang, Yung-Hsu Chuang, Shu-Chin Tai, Wen-Shen Chou, Yung-Chow Peng
  • Publication number: 20250086857
    Abstract: An unreal engine graphic construction method includes the following steps: receiving data to be displayed; determining a number N of basic graphics contained in a graphic to be constructed according to the data to be displayed, wherein, N>1; calling an underlying function at a blueprint layer to draw N of the basic graphics in sequence, wherein the underlying function is used for creating the basic graphics.
    Type: Application
    Filed: December 21, 2022
    Publication date: March 13, 2025
    Inventors: Danfeng ZHU, Zhe ZHANG, Xiao CHU, Naichuan CHEN, Sujia JIANG, Hongxiang SHEN, Ming GU
  • Patent number: 12249568
    Abstract: A metallization structure electrically connected to a conductive bump is provided. The metallization structure includes an oblong-shaped or elliptical-shaped redistribution pad, a conductive via disposed on the oblong-shaped or elliptical-shaped redistribution pad, and an under bump metallurgy covering the conductive via, wherein the conductive bump is disposed on the UBM. Furthermore, a package structure including the above-mentioned metallization structures is provided.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 12249539
    Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: March 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Wen Shen, Jiun-Ming Kuo, Yuan-Ching Peng, Ji-Xuan Yang, Jheng-Wei Lin, Chien-Hung Chen
  • Publication number: 20250079414
    Abstract: An electronic package module and a method for fabrication of the same are provided. The method includes providing an electronic component assembly and a circuit substrate. The electronic component assembly includes two electronic components and a conductive structure. The electronic components are connected to each other through a conductive adhesive material, while the electronic components are connected to the conductive structure through another conductive adhesive material. A soldering material is formed on the circuit substrate, and the electronic component assembly is disposed on the soldering material. The melting points of the conductive adhesive materials are higher than the melting point of the soldering material. As a result, the conductive adhesive materials are prevented from failure during the soldering process, and thus the process yield is improved.
    Type: Application
    Filed: January 16, 2024
    Publication date: March 6, 2025
    Inventors: KUO-HSIEN LIAO, LI-CHENG SHEN, HUNG-YI TSAI, CHAO-HSUAN WANG, CHUN-MING CHEN, TAI-LIN WU, CHIH-SHIEN CHEN, PING-CHI HUNG
  • Patent number: D1070862
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: April 15, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Fu-Yu Cai, Chun-Fu Chen, Che-Hsiung Chao, Ming-Chih Huang, Tong-Shen Hsiung, Shang-Chih Liang