Abstract: A semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.

Abstract: A lens module including an integrated lens holder and a lens group is provided. The lens holder is composed of a fixed piece and a lens frame. The lens frame is connected to the fixed piece. The lens frame includes an accommodating cavity and a bearing surface located in a periphery of the accommodating cavity. The lens group is disposed in the accommodation cavity and is supported on the bearing surface.

Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized to transmit and receive optical signals to and from an optical device. In embodiments the mirror structure receives optical signals from outside of an optical device and directs the optical signals through at least one mirror to an optical component of the optical device.

Abstract: Methods of designing integrated circuits incorporating an analog ECO flow are provided. An example method comprises receiving an initial design and performing an auto-marker process. The auto-marker process comprises performing a first auto-marker process to surround a first plurality of active cells of the design with first computer-aided design (CAD) layers corresponding to a first plurality of engineering change order (ECO) cells, performing an enhanced auto-marker process to cover irregular shapes of the design with second CAD layers corresponding to a second plurality of ECO cells, and performing a second auto-marker process to fill empty areas of the design with third CAD layers corresponding to a third plurality of ECO cells. The method further includes filling the design with the first plurality of ECO cells, the second plurality of ECO cells, and the third plurality of ECO cells.

Abstract: A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.

Abstract: An unreal engine graphic construction method includes the following steps: receiving data to be displayed; determining a number N of basic graphics contained in a graphic to be constructed according to the data to be displayed, wherein, N>1; calling an underlying function at a blueprint layer to draw N of the basic graphics in sequence, wherein the underlying function is used for creating the basic graphics.

Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.

Abstract: A metallization structure electrically connected to a conductive bump is provided. The metallization structure includes an oblong-shaped or elliptical-shaped redistribution pad, a conductive via disposed on the oblong-shaped or elliptical-shaped redistribution pad, and an under bump metallurgy covering the conductive via, wherein the conductive bump is disposed on the UBM. Furthermore, a package structure including the above-mentioned metallization structures is provided.

Abstract: A power semiconductor device, including a cell region, a transition region, and a terminal region. The transition region is located between the cell region and the terminal region of the device. A first conduction type substrate, a first conduction type epitaxial layer located above the first conduction type substrate, and a first conduction type buffer layer located in the first conduction type epitaxial layer are jointly arranged at the bottoms of the cell region, the transition region, and the terminal region of the device. In a high-current application, since the cell region occupies the largest area of a chip, in a case that breakdown can occur in the cell region and the current can be discharged through the cell region. On the basis of ensuring the BV of the terminal region, a silicon layer step is formed by elevating the position of a top structure of the terminal region.

Abstract: The present disclosure discloses an SoC chip distributed simulation and verification platform and a method, and the present disclosure relates to the field of chip verification technologies. The distributed simulation and verification platform includes component modules of an SoC chip; each module has its own verification platform, and each verification platform separately runs in a different simulation process; and virtual connections between the modules are implemented through respective verification platforms, to implement system function simulation and verification. In the present disclosure, a virtual connection technology is used to connect Testbench test platforms of the modules or IPs, to implement virtual integration of the modules or IPs, thereby completing distributed simulation and verification of a system function of the SoC chip.

Abstract: A wireless network apparatus and a communication method are provided. The wireless network apparatus transmits signals through a channel and an access point, and includes a radio frequency transceiver and a control circuit. The control circuit is configured to execute a communication procedure, which includes processes of: activating the radio frequency transceiver to receive a beacon sent by the access point through the channel, and determining whether or not the radio frequency transceiver receives the beacon; determining, in response to determining that the radio frequency transceiver does not receive the beacon, whether or not the channel satisfies a predetermined condition by an energy detection circuit; and deactivating, in response to determining that the channel satisfies the predetermined condition, the radio frequency transceiver.

Abstract: An electronic package module and a method for fabrication of the same are provided. The method includes providing an electronic component assembly and a circuit substrate. The electronic component assembly includes two electronic components and a conductive structure. The electronic components are connected to each other through a conductive adhesive material, while the electronic components are connected to the conductive structure through another conductive adhesive material. A soldering material is formed on the circuit substrate, and the electronic component assembly is disposed on the soldering material. The melting points of the conductive adhesive materials are higher than the melting point of the soldering material. As a result, the conductive adhesive materials are prevented from failure during the soldering process, and thus the process yield is improved.

Abstract: An optical device for preventing dew condensation including a housing, a transparent glass and a lens structure is provided. The housing has a first permeable portion capable of communicating between an interior and an exterior of the housing. The transparent glass has an inner surface and is coupled to the housing with the inner surface facing the interior of the housing. The lens structure is accommodated in the housing, and a chamber is formed between the lens structure, the housing and the inner surface of the transparent glass. The chamber and the exterior of the housing are capable of forming an airflow path therebetween, and the airflow path is adjustable to control whether an airflow is able to enter and exit the chamber and the exterior of the housing through the first permeable portion.

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, semiconductor dies over the package substrate, and an underfill element over the package substrate and surrounding the semiconductor dies. A portion of the underfill element is located between the semiconductor dies. The semiconductor die package also includes lid structures respectively attached to the top surfaces of the semiconductor dies. In plan view, each lid structure is located within the periphery of the top surface of the corresponding semiconductor die. Each lid structure is disconnected from other lid structures, and a gap is formed between adjacent lid structures and located over the portion of the underfill element.

Abstract: There is provided an optical machine of a smoke detector including a substrate, a light source, a light sensor and a light blocking member. The light source and the light sensor are arranged on the substrate in a first direction. The light blocking member is arranged upon the light source and blocks a part of an emission angle of the light source in the first direction far away from the light sensor.

Abstract: A light-emitting package, includes: a housing including an opening; a lead frame covered by the housing; a light-emitting device, mounted in the opening and electrically connected to the lead frame, the light-emitting device including: a substrate including: a base with a main surface; and a plurality of protrusions on the main surface, wherein the protrusion and the base include different materials; a semiconductor stack on the main surface, the semiconductor stack including a side wall, and wherein an included angle between the side wall and the main surface is an obtuse angle; wherein the main surface includes a peripheral area not covered by the semiconductor stack, and the peripheral area is devoid of the protrusion formed thereon; and a filling material filling in the opening and covering the light-emitting device.

Abstract: A package structure is provided. The package structure includes a semiconductor die over a redistribution structure, bonding elements below the redistribution structure, and an underfill layer surrounding the bonding elements and the redistribution structure. The semiconductor die has a rectangular profile in a plan view. A pitch of the bonding elements is defined as the sum of a diameter of the bonding elements and a spacing between neighboring two of the bonding elements. A first circular area of the redistribution structure is entirely covered and in direct contact with the underfill layer. The center of the first circular area is aligned with a first corner of the rectangular profile of the semiconductor die. A diameter of the first circular area is greater than twice the pitch of the bonding elements.

Abstract: A fan-out package includes a redistribution structure having redistribution-side bonding structures, a plurality of semiconductor dies including a respective set of die-side bonding structures that is attached to a respective subset of the redistribution-side bonding structures through a respective set of solder material portions, and an underfill material portion laterally surrounding the redistribution-side bonding structures and the die-side bonding structures of the plurality of semiconductor dies. A subset of the redistribution-side bonding structures is not bonded to any of the die-side bonding structures of the plurality of semiconductor dies and is laterally surrounded by the underfill material portion, and is used to provide uniform distribution of the underfill material during formation of the underfill material portion.

Abstract: A machine vision-based sheet defect labeling method and apparatus, a device and a medium are provided. The method includes: performing a defect inspection on a target sheet conveyed to a preset defect inspection position, specifically, the target sheet continues to be conveyed towards a preset labeling position after passing the preset defect inspection position by being conveyed; generating a defect label of the target sheet when a defect present in the target sheet is determined, specifically, the defect label carries defect information represented by a two-dimensional barcode symbol including discontinuous dots; and labeling the defect of the target sheet at the preset labeling position with the defect label of the target sheet.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.