Abstract: The current disclosure includes a plasma etching system that includes a movable plasma source and a moveable wafer stage. A relative position between the movable plasma source and the movable wafer stage can be varied to set up an angle along which plasma particles of the plasma hits a wafer positioned on the wafer stage.

Abstract: A method of forming a semiconductor device includes following steps. A sacrificial layer is formed in an opening of a substrate. A first doped region is formed in the opening over the sacrificial layer. The substrate is flipped. A portion of the substrate is removed to expose the sacrificial layer. The sacrificial layer is replaced with a first contact.

Abstract: Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

Abstract: A semiconductor structure includes a third metal layer immediately above a second metal layer that is over a first metal layer. The second metal layer includes magnetic tunneling junction (MTJ) devices in a memory region and a first conductive feature in a logic region. Each MTJ device includes a bottom electrode and an MTJ stack over the bottom electrode. The third metal layer includes a first via electrically connecting to the first conductive feature, and a slot via over and electrically connecting to the MTJ stack of the MTJ devices. The slot via occupies space extending continuously and laterally from a first one to a last one of the MTJ devices. The first via is as thin as or thinner than the slot via. The third metal layer further includes second and third conductive features electrically connecting to the first via and the slot via, respectively.

Abstract: The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.

Abstract: A fan-out package includes a redistribution structure having redistribution-side bonding structures, a plurality of semiconductor dies including a respective set of die-side bonding structures that is attached to a respective subset of the redistribution-side bonding structures through a respective set of solder material portions, and an underfill material portion laterally surrounding the redistribution-side bonding structures and the die-side bonding structures of the plurality of semiconductor dies. A subset of the redistribution-side bonding structures is not bonded to any of the die-side bonding structures of the plurality of semiconductor dies and is laterally surrounded by the underfill material portion, and is used to provide uniform distribution of the underfill material during formation of the underfill material portion.

Abstract: The problem of providing transistors that can be manufactured to any specified threshold voltage withing a broad range of threshold voltages without creating leakage, capacitance, or process compatibility issues is solved by introducing a buried layer of a second dielectric composition into a gate dielectric of a first dielectric composition. The second dielectric composition is selected relative to the first dielectric composition so that dipoles form around the interface of the two dielectrics. The dipoles create an electric field that causes a shift in the threshold voltage. The buried layer has a higher dielectric constant than the gate dielectric, is thinner than the gate dielectric, and is proximate the channel.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: A method of forming a semiconductor device package is provided. The method includes bonding a first package component and a second package component to a substrate, wherein the first and second package components are different types of electronic components that provide different functions; attaching at least one dummy die to the substrate, wherein the dummy die is electrically isolated from the substrate, wherein the first and second package components are disposed on two opposite sides of the dummy die; and disposing an underfill element between the substrate, the first package component, the second package component, and the dummy die, wherein the underfill element extends up along the sidewalls of the dummy die and laterally surrounds the sidewalls of the dummy die in a top view, wherein the underfill element has a maximum height lower than the top surface of the dummy die.

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

Abstract: In one aspect, compounds of Formula AA, or a pharmaceutically acceptable salt thereof, are featured or a pharmaceutically acceptable salt thereof, wherein the variables shown in Formula A can be as defined anywhere herein.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A radiation protection arrangement, including: a housing, the housing including a first port and a second port; and a tray, the tray having an accommodation space. The tray is allowed to pass through a channel within the housing. The tray has a first end wall, a second end wall, and a bottom portion connected between the first end wall and the second end wall. A shape of the first end wall and/or a shape of the second end wall are/is configured to fit with an inner wall of the housing, so as to block a radiation from leaving the channel from the accommodation space through the second port or the first port. Further provided is a security inspection device, including the radiation protection arrangement.

Abstract: The present disclosure is a three-way U-Net method for accurately segmenting an uncertain boundary of a retinal blood vessel, includes: describing an uncertainty of a blood vessel boundary label, constructing an upper bound and a lower bound of the uncertain boundary based on the dilation operator and the erosion operator respectively to obtain a maximum value and a minimum value for the blood vessel boundary, and mapping the boundary with uncertain information into one range; combining an uncertainty representation of the boundary with a loss function, and designing a three-way loss function; training network parameters by adopting a stochastic gradient descent algorithm and utilizing a total loss of the three-way loss function; and designing and implements an auxiliary diagnosis application system for intelligently segmenting the retinal blood vessel with functions of the fundus data acquisition, the intelligent accurate segmentation and the auxiliary diagnosis for the retinal blood vessel.

Abstract: The present disclosure provides an electronic shelf label, including a rear shell (1), a screen (4), a protective sheath (5) and a lens (6). The protective sheath (5) is sheathed on an outer side of the screen (4), an accommodation groove (101) is formed on the rear shell (1), and the screen (4) is disposed in the accommodation groove (101). The lens (6) is disposed to cover a groove opening of the accommodation groove (101) and is connected to an edge of the rear shell (1). A portion of the protective sheath (5) located at an edge of a display port of the screen (4) is supported between the lens (6) and the screen (4), so that a press-resistant gap (8) is reserved between the lens (6) and the screen (4). The present disclosure solves the technical problems that the electronic shelf label is easy to be damaged and the use effect is poor.

Abstract: A jobsite audio device with multi-source power and multi-port USB interface is proposed, which includes an AC-DC power source, a battery pack, a multi-port USB interface including at least one bidirectional power delivery USB C port, a charging circuit coupled to the AC-DC power source, the battery pack and the multi-port USB interface to provide power delivery paths, an audio module powered by the AC-DC power source or the battery pack to generate audio signals, and a main controller coupled to the charging circuit and the audio module, wherein the main controller monitors power consumption of the audio module and charging process of the charging circuit to automatically adjust charging power.

Abstract: A light sensor includes an optoelectronic device and a light guide element. The light guide element has a first light incident surface and a light exit surface, so as to allow an incident light to enter the light guide element from the first light incident surface and then exit to the optoelectronic device from the light exit surface; wherein at least one of the light incident surface and the light exit surface has a single curved surface.

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.

Abstract: A segmental precast composite-material composite-slab composite beam and a construction method thereof are provided, relating to the technical field of bridge design and construction. The segmental precast composite-material composite-slab composite beam mainly includes a segmental precast orthotropic composite top slab, a web, a bottom slab, and a wet joint between segments. The orthotropic composite top slab is composed of an orthotropic slab and an ultra-high-performance concrete layer (UHPC), and the interface connection of the orthotropic slab and the UHPC structural layer is achieved by a shear key. The UHPC structural layer is superposed with the orthotropic slab in segments in a precast plant to form a composite-slab composite beam segment to be entirely transported, hoisted and assembled, and the connection of the UHPC structural layers between the segments is achieved by casting a transverse wet joint in place.

Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.