Abstract: A interconnect structure and the method for fabricating the same is disclosed in this present invention. By employing a metallic compound layer, the adhesion of the cap layer to the metal layer according to this invention can be improved, and metal migration due to thermal stress in the prior art will not occur in the interconnect structure according to this invention. Furthermore, the interconnect structure and the method for manufacturing the same can efficiently keep the interconnect structure from occurring metal migration, thus no voids from thermal stress will be formed in the interconnect structure. Hence, this invention can prevent the interconnect structure from raising the resistance of the interconnect structure by the voids, and efficiently improve the reliability of the interconnect in a semiconductor structure.

Abstract: A interconnect structure and the method for fabricating the same is disclosed in this present invention. By employing a metallic compound layer, the adhesion of the cap layer to the metal layer according to this invention can be improved, and metal migration due to thermal stress in the prior art will not occur in the interconnect structure according to this invention. Furthermore, the interconnect structure and the method for manufacturing the same can efficiently keep the interconnect structure from occurring metal migration, thus no voids from thermal stress will be formed in the interconnect structure. Hence, this invention can prevent the interconnect structure from raising the resistance of the interconnect structure by the voids, and efficiently improve the reliability of the interconnect in a semiconductor structure.

Abstract: A semiconductor wafer is provided, which has a low k layer positioned on the semiconductor wafer and a dual damascene structure positioned in the low k layer. The dual damascene structure includes a trench and a via hole, the via hole connecting to a conductive layer laid beneath. A barrier layer is formed at a temperature of 300 to 400° C. to cover the dual damascene structure and the low k layer. Thereafter, the semiconductor wafer is cooled to room temperature.

Abstract: A method for forming metal interconnects. A substrate having a metal line is provided. A dielectric layer with an opening exposing the metal line is formed over the substrate, which dielectric layer further comprises an etching stop layer. After forming a covering layer conformal to a profile of the opening over the substrate, a portion of the covering layer in a bottom of the opening is removed to expose the metal line. A conformal barrier layer and a metal layer are formed sequentially in the opening and the metal layer fills up the opening. After forming a cap layer covering the substrate, the cap layer and the dielectric layer are defined to form a second opening. Next, remove the dielectric layer exposed by the opening, thus forming air-gaps.