Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Abstract: In an electronic data storage device accessed by a host computer motherboard, a fingerprint sensor scans a fingerprint of a user of the electronic data storage device and generates fingerprint scan data. A processing unit activates an input/output interface circuit to store a data file and fingerprint reference data obtained by scanning a fingerprint of a person authorized to access the data file in a memory device having non-volatile memory, where the processing unit transmits the data file to the host computer motherboard upon verifying that the user of the electronic data storage device is authorized to access the data file stored in the memory device as a result of comparison between the fingerprint scan data from the fingerprint sensor and the fingerprint reference data. Other methods and apparatuses are also described.

Abstract: A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.

Abstract: A Bose, Ray-Chaudhuri, Hocquenghem (BCH) decoder is employed in non-volatile memory applications for determining the number of errors and locating the errors in a page of information. The decoder includes a syndrome calculator responsive to a sector of information. The sector includes data and overhead, with the data being organized into data sections and the overhead being organized into overhead sections. The syndrome calculator generates a syndrome for each of the data sections. A root finder is coupled to receive the calculated syndrome and to generate at least two roots. A polynomial calculator responds to the two roots and generates at least two error addresses, each identifying a location in the data wherein the error lies.

Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Abstract: A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.

Abstract: Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Abstract: A multi-partition Universal Serial Bus (USB) device has a flash memory with multiple partitions of storage. Some partitions are for different operating systems and store OS images. Another partition has a control program while a user partition stores user data and user configuration information. The control program can test the multi-partition USB device and instruct the host computer BIOS to mount a partition from its flash memory as a drive of the host computer. The host computer can then be rebooted. The OS image from the flash memory is loaded into main memory during rebooting, and the host computer executes a new operating system using the new OS image. The user can press buttons on the multi-partition USB device to select which OS to load, and to begin rebooting. Virus removal programs in the alternate OS can help recover from a virus in the primary OS.

Abstract: One embodiment of the present includes a electronic data storage card having a Reed Solomon (RS) decoder having a syndrome calculator block responsive to a page of information, the page being organized into a plurality of data sections and the overhead being organized into a plurality of overhead sections. The syndrome calculator generates a syndrome for each of the data sections. The decoder further includes a root finder block responsive to the calculated syndrome and for generating at least two roots, a polynomial calculator block responsive to the at least two roots and operative to generate at least one error address, identifying a location in the data wherein the error lies, and an error symbol values calculator block coupled to the root finder and the polynomial calculator block and for generating a second error address, identifying a second location in the data wherein the error(s) lie.

Abstract: Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Abstract: Non-volatile memory based computer systems and methods are described. According to one aspect of the invention, at least one non-volatile memory module is coupled to a computer system as main storage. The non-volatile memory module is controlled by a northbridge controller configured to control the non-volatile memory as main memory. The page size of the at least one non-volatile memory module is configured to be the size of one of the cache lines associated with a microprocessor of the computer system. According to another aspect, at least one non-volatile memory module is coupled to a computer system as data read/write buffer of one or more hard disk drives. The non-volatile memory module is controlled by a southbridge controller configured to control the non-volatile memory as an input/out device. The page size of the at least one non-volatile memory module is configured in proportion to characteristics of the hard disk drives.

Abstract: A Universal Serial Bus (USB) memory card includes a tube metal housing that is rectangularly-shaped and a Chip-On-Board (COB)-Universal Serial Bus (USB) device and a carrier substrate having a U-block disposed on one side of thereof and vertically extending upwardly from a bottom surface of the U-block, the COB-USB device positioned on the carrier substrate forming a USB card sub-assembly, the USB card sub-assembly being securely located inside the metal housing with the U-block serving to stop the COB-USB device from slipping out of the metal housing.

Abstract: According to certain embodiments of the invention, a single chip COB USB manufacturing is using chip-on-board (COB) processes on a PCB panel with multiple individual USB PCB substrates. This single chip COB USB is laid out in an array of N×M matrixes. The advantages of this method are: 1) use molding over PCBA, versus conventional of using SMT process to mount all necessary component on substrate to form PCBA; 2) simpler rectangular structure to fit any external decorative shell package for added value; and 3) package is moisture resistance if not water proof.

Abstract: High integration of a non-volatile memory device (NVMD) is disclosed. According to one aspect of the present invention, a non-volatile memory device comprises an intelligent non-volatile memory (NVM) controller and an intelligent non-volatile memory module. The NVM controller includes a central processing unit (CPU) configured to handle data transfer operations to the NVM module to ensure source synchronous interface, interleaved data operations and block abstracted addressing. The intelligent NVM module includes an interface logic, a block address manager and at least one non-volatile memory array. The interface logic is configured to handle physical block management. The block address manager is configured to ensure a physical address is converted to a transformed address that is accessible to the CPU of the intelligent NVM controller. The transformed address may be an address in blocks, pages, sectors or bytes either logically or physically.

Abstract: A low-profile Universal-Serial-Bus (USB) device includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts. The IC chips include, for example, a USB controller chip and a flash memory chip, or a single-chip (combined USB controller/flash memory) chip. Multiple flash IC chips are optionally stacked to increase storage capacity. The IC chip(s) are attached to the PCB by wire bonding or other chip-on-board (COB) technique. The passive components are attached by conventional surface mount technology (SMT) techniques. A molded housing is then formed over the IC chips and passive components such that the device has a uniform thickness. The low-profile USB device is optionally used as a modular insert that is mounted onto a metal case to provide a USB assembly having a plug shell similar to a standard USB male connector.

Abstract: An electronic data flash card includes a random number generator that generates a random number stored in the card and a host system each time the card is accessed by the host system. The random number is used by the host system to encrypt a logical branch address, a user password, and user data that is written to and stored in a secure area of the card. The random number is encrypted using a key associated with the card, and the encrypted random number is stored by the card with the associated encrypted data. The random number is not stored in the host system. A new random number is generated each time the card is queried. In a read process the host system decrypts the encrypted random number using the key, then uses the random number to decrypt the associated encrypted data. Access to read/write processes are password protected.

Abstract: An extended USB plug connector includes a connector substrate including a frontend having a first set of electrical contact pins disposed thereon and a backend having a second set of electrical contact pins disposed thereon. The first set includes a first row of electrical contact pins disposed on a top surface of the connector substrate and a second row of electrical contact pins disposed in parallel with the first row of electrical contact pins and interior to the first row of electrical contact pins, where the second row includes more electrical contact pins than the first row. The second set of electrical contact pins includes a number of electrical contact pins equal to the first row and second row of electrical contact pins in total. The second set of electrical contact pins are used to connect to corresponding electrical contact pads disposed on a printed circuit board assembly having a USB controller and flash memory devices disposed thereon.

Abstract: Data error detection and correction in non-volatile memory devices are disclosed. Data error detection and correction can be performed with software, hardware or a combination of both. Generally an error corrector is referred to as an ECC (error correction code). One of the most relevant codes using in non-volatile memory devices is based on BCH (Bose, Ray-Chaudhuri, Hocquenghem) code. In order to correct reasonable number (e.g., up to 8-bit (eight-bit)) of random errors in a chunk of data (e.g., a codeword of 4200-bit with 4096-bit information data), a BCH(4200,4096,8) is used in GF(213). ECC comprises encoder and decoder. The decoder further comprises a plurality of error detectors and one error corrector. The plurality of error decoders is configured for calculating odd terms of syndrome polynomial for multiple channels in parallel, while the error corrector is configured for sequentially calculating even terms of syndrome polynomial, key solver and error location.

Abstract: A portable media player receives encrypted audio files and an encrypted content key from a central license server on the Internet. The media player supports digital rights management (DRM) by storing the encrypted audio file in its flash memory and disabling copying or playing of the audio file after a copy limit has been reached. The copy limit is a rule that is combined with the content key in a transfer key that can be encrypted together by the license server. The license server can detect cloning of the media player by reading a unique player ID from the player and detecting when too many accounts use the same unique player ID. The content key can be generated from polar coordinates of the unique player ID, player manufacturer, and song genre. A fingerprint sensor on the player can scan and compare the user's fingerprints to further detect cloning.

Abstract: A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Supporting end ribs under each of the SD contact pads and middle ribs support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline.