Patents by Inventor Ming-Shih Yeh
Ming-Shih Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10290610Abstract: A PoP device includes a first package structure, a second package structure and an underfill layer is provided. The first package structure includes a die, a TIV and an encapsulant. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and a portion of sidewalls of the TIV. The second package structure is connected to the first package structure through a connector. The underfill layer is disposed to fill a space between the first package structure and the second package structure. A portion of the underfill layer is disposed between the encapsulant and the TIV to cover a portion of sidewalls of the TIV.Type: GrantFiled: August 29, 2017Date of Patent: May 14, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Li-Hui Cheng, Po-Hao Tsai, Wei-Yu Chen, Ming-Shih Yeh
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Publication number: 20190131283Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.Type: ApplicationFiled: October 27, 2017Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
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Publication number: 20190115300Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.Type: ApplicationFiled: December 17, 2018Publication date: April 18, 2019Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu
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Publication number: 20190067249Abstract: A PoP device includes a first package structure, a second package structure and an underfill layer is provided. The first package structure includes a die, a TIV and an encapsulant. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and a portion of sidewalls of the TIV. The second package structure is connected to the first package structure through a connector. The underfill layer is disposed to fill a space between the first package structure and the second package structure. A portion of the underfill layer is disposed between the encapsulant and the TIV to cover a portion of sidewalls of the TIV.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Li-Hui Cheng, Po-Hao Tsai, Wei-Yu Chen, Ming-Shih Yeh
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Publication number: 20190035772Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.Type: ApplicationFiled: July 27, 2017Publication date: January 31, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsien Huang, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hua-Wei Tseng, Ming-Chih Yew, Yi-Jen Lai, Ming-Shih Yeh
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Patent number: 10163803Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first die, at least one through integrated fan-out via and a molding layer. The at least one through integrated fan-out via is aside the first die and includes a seed layer and a metal layer. The molding layer encapsulates the at least one through integrated fan-out via and the first die. Besides, the seed layer surrounds a sidewall of the metal layer and is between the metal layer and the molding layer.Type: GrantFiled: June 20, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming-Shih Yeh
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Publication number: 20180366410Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first die, at least one through integrated fan-out via and a molding layer. The at least one through integrated fan-out via is aside the first die and includes a seed layer and a metal layer. The molding layer encapsulates the at least one through integrated fan-out via and the first die. Besides, the seed layer surrounds a sidewall of the metal layer and is between the metal layer and the molding layer.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming-Shih Yeh
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Patent number: 10157852Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.Type: GrantFiled: June 29, 2018Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu
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Publication number: 20180323150Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.Type: ApplicationFiled: June 29, 2018Publication date: November 8, 2018Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu
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Publication number: 20180226349Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.Type: ApplicationFiled: July 3, 2017Publication date: August 9, 2018Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu
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Publication number: 20180211912Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.Type: ApplicationFiled: July 3, 2017Publication date: July 26, 2018Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kou
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Patent number: 9224643Abstract: The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively.Type: GrantFiled: September 19, 2011Date of Patent: December 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ju Lee, Tien-I Bao, Ming-Shih Yeh, Hai-Ching Chen, Shau-Lin Shue
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Patent number: 8987085Abstract: A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.Type: GrantFiled: September 20, 2006Date of Patent: March 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Shih Yeh, Chih-Hsien Lin, Yung-Cheng Lu, Hui-Lin Chang
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Patent number: 8623760Abstract: An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.Type: GrantFiled: April 5, 2012Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsueh Shih, Minghsing Tsai, Chen-Hua Yu, Ming-Shih Yeh
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Patent number: 8432040Abstract: An interconnection structure for integrated circuits having reduced RC delay and leakage is provided. The interconnection structure includes a first conductive line in a first dielectric layer, a second dielectric layer over the first dielectric layer and the first conductive line, and a dual damascene structure in the second dielectric layer. The dual damascene structure includes a second conductive line and a via between and adjoining the first and the second conductive lines, wherein the second conductive line comprises a first portion directly over and adjoining the via, and a second portion having no underlying and adjoining vias. The second portion has a second width less than a first width of the first portion.Type: GrantFiled: June 1, 2006Date of Patent: April 30, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming-Shih Yeh
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Publication number: 20130069234Abstract: The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively.Type: ApplicationFiled: September 19, 2011Publication date: March 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ju Lee, Tien-I Bao, Ming-Shih Yeh, Hai-Ching Chen, Shau-Lin Shue
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Publication number: 20120190191Abstract: An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.Type: ApplicationFiled: April 5, 2012Publication date: July 26, 2012Applicant: Taiwan Semiconductor Manufaturing Company, Ltd.Inventors: Chien-Hsueh Shih, Minghsing Tsai, Chen-Hua Yu, Ming-Shih Yeh
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Patent number: 8193087Abstract: An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.Type: GrantFiled: November 28, 2006Date of Patent: June 5, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hsueh Shih, Minghsing Tsai, Chen-Hua Yu, Ming-Shih Yeh
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Patent number: 8109407Abstract: An apparatus includes an enclosure and a door configured to seal the enclosure. The door includes a plate. A rotational apparatus is disposed over the plate. At least one first member with a first arm extends from a first rib of the first member. At least one second member with a second arm extends from a second rib of the second member. The first and second arms are connected to the rotational apparatus. At least one corner member has a first edge. The first edge has a shape corresponding to a shape of a corner of the frame. The corner member is connected to a first end of the third arm. A second end of the third arm is connected to the rotational apparatus. A sealing material is disposed along a first longitudinal side of the first rib and a second longitudinal side of the second rib.Type: GrantFiled: May 30, 2007Date of Patent: February 7, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Li Hsiao, Chen-Hua Yu, Jean Wang, Jui-Pin Hung, Ming-Shih Yeh
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Patent number: 8106512Abstract: The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.Type: GrantFiled: July 29, 2010Date of Patent: January 31, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiang-Huan Lee, Ming Han Lee, Ming-Shih Yeh, Chen-Hua Yu, Shau-Lin Shue