Abstract: An automatic switching phase-locked loop (PLL) is disclosed, including a phase detector, a charge pump generating a pump current, a band selector receiving a control voltage to produce a band selection signal and a voltage setting signal based the control voltage, a loop filter generating the control voltage corresponding to the pump current and setting the control voltage based on the voltage setting signal, and a multi-band voltage control oscillator (VCO) coupled to the control voltage and the band selection signal, selecting one of a plurality of operating bands based on the band selection signal, and providing an output signal of a frequency within the selected operating band based on the control voltage.

Abstract: An automatic switching phase-locked loop (PLL) is disclosed, including a phase detector, a charge pump generating a pump current, a band selector receiving a control voltage to produce a band selection signal and a voltage setting signal based the control voltage, a loop filter generating the control voltage corresponding to the pump current and setting the control voltage based on the voltage setting signal, and a multi-band voltage control oscillator (VCO) coupled to the control voltage and the band selection signal, selecting one of a plurality of operating bands based on the band selection signal, and providing an output signal of a frequency within the selected operating band based on the control voltage.

Abstract: The present invention discloses a delay-locked loop device capable of anti-false-locking, which comprises: a voltage control delay circuit comprising a plurality of delay units in a series for generating a delayed phase according to a reference phase and a control voltage; a phase detector coupled to the voltage control delay circuit for generating a control signal according to a lock indication signal, the reference phase, and the delayed phase; a charge pump coupled to the phase detector for transmitting the control voltage to the voltage control delay circuit according to the control signal; and a lock detector coupled to the voltage control delay circuit for generating the lock indication signal for the phase detector according to output phases of at least one delay unit of the voltage control delay circuit.

Abstract: A hysteresis current comparator includes a first current comparison unit, a second current comparison unit, and a control circuit connected to the two current comparison units. The first current comparison unit compares a first reference current with an input current and outputs a first voltage accordingly. The second current comparison unit compares a second reference current with the input current and outputs a second voltage accordingly. The control circuit generates an output voltage according to the voltages output by the two current comparison units, or generates an output voltage according to the voltages output by the two current comparison units and the output voltage of the control circuit at a former state.

Abstract: The present invention discloses a delay-locked loop device capable of anti-false-locking, which comprises: a voltage control delay circuit comprising a plurality of delay units in a series for generating a delayed phase according to a reference phase and a control voltage; a phase detector coupled to the voltage control delay circuit for generating a control signal according to a lock indication signal, the reference phase, and the delayed phase; a charge pump coupled to the phase detector for transmitting the control voltage to the voltage control delay circuit according to the control signal; and a lock detector coupled to the voltage control delay circuit for generating the lock indication signal for the phase detector according to output phases of at least one delay unit of the voltage control delay circuit.

Abstract: A hysteresis current comparator includes a first current comparison unit, a second current comparison unit, and a control circuit connected to the two current comparison units. The first current comparison unit compares a first reference current with an input current and outputs a first voltage accordingly. The second current comparison unit compares a second reference current with the input current and outputs a second voltage accordingly. The control circuit generates an output voltage according to the voltages output by the two current comparison units, or generates an output voltage according to the voltages output by the two current comparison units and the output voltage of the control circuit at a former state.

Abstract: A delay-locked loop device capable of anti-false-locking includes a voltage control delay circuit including a plurality of delay units in a series for generating a delayed phase according to a reference phase and a control voltage; a phase detector coupling to the voltage control delay circuit for generating a control signal according to a lock indication signal, the reference phase, and the delayed phase; a charge pump coupling to the phase detector for generating the control voltage to the voltage control delay circuit according to the control signal; and a lock detector coupling to the voltage control delay circuit for generating the lock indication signal for the phase detector according to output phases of each delay unit of the voltage control delay circuit.