Patents by Inventor Ming SHU
Ming SHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979548Abstract: A structured light projector is disclosed, which includes a first light source, a second light source, an optical refractive element and an optical shaper. The first light source and the second light source are configured to respectively emit first incoherent light and second incoherent light. The optical refractive element is arranged over the first and second light sources for refracting the first incoherent light and the second incoherent light. The optical shaper element is arranged over the optical refractive element for shaping the first incoherent light to generate first structured light with plural first optical patterns and shaping the second incoherent light to generate second structured light with plural second optical patterns, in which the first structured light and the second structured light are overlapped onto a region of space.Type: GrantFiled: April 8, 2022Date of Patent: May 7, 2024Assignee: HIMAX TECHNOLOGIES LIMITEDInventor: Ming-Shu Hsiao
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Publication number: 20240147714Abstract: The present disclosure relates to a method of forming a flash memory structure. The method includes forming a sacrificial material over a substrate, and forming a plurality of trenches extending through the sacrificial material to within the substrate. A dielectric material is formed within the plurality of trenches. The dielectric material is selectively etched, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches. The sacrificial material between neighboring ones of the depressions is removed to form a floating gate recess. A floating gate material is formed within the floating gate recess and the neighboring ones of the depressions.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: Hung-Shu Huang, Ming Chyi Liu
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Patent number: 11924080Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network and multiple host computers executing multiple machines. At a first host computer, the method identifies and stores (i) multiple time values associated with several packet processing operations performed on a particular packet sent by a first machine executing on the first host computer, and (ii) a time value associated with packet transmission through the SDDC network from the first host computer to a second host computer that is a destination of the particular packet. The method provides the stored time values to a set of one or more controllers to process to identify multiple latencies experienced by multiple packets processed in the SDDC.Type: GrantFiled: March 21, 2022Date of Patent: March 5, 2024Assignee: VMware LLCInventors: Haoran Chen, Ming Shu, Xi Cheng, Feng Pan, Xiaoyan Jin, Caixia Jiang, Qiong Wang, Qi Wu
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Publication number: 20240033350Abstract: The present disclosure relates to a vaccine composition, comprising a recombinant lipidated FLIPr (rLF), and the use thereof in enhancing humoral and cellular immune responses. The recombinant lipidated FLIPr of present invention may be used as a vaccine candidate that can induce anti-FLIPr responses to overcome FLIPr-mediated inhibition. And unexpectedly, the recombinant lipidated FLIPr may be used as an adjuvant that can enhance other vaccine immune responses, especially in subunit vaccines and inactivated virus vaccines.Type: ApplicationFiled: August 1, 2023Publication date: February 1, 2024Inventors: Hsin-Wei CHEN, Ming-Shu HSIEH, Shih-Jen LIU, Ching-Len LIAO
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Patent number: 11862727Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.Type: GrantFiled: December 29, 2022Date of Patent: January 2, 2024Assignee: United Microelectronics Corp.Inventors: Hao Che Feng, Hung Jen Huang, Hsin Min Han, Shih-Wei Su, Ming Shu Chiu, Pi-Hung Chuang, Wei-Hao Huang, Shao-Wei Wang, Ping Wei Huang
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Publication number: 20230328218Abstract: A structured light projector is disclosed, which includes a first light source, a second light source, an optical refractive element and an optical shaper. The first light source and the second light source are configured to respectively emit first incoherent light and second incoherent light. The optical refractive element is arranged over the first and second light sources for refracting the first incoherent light and the second incoherent light. The optical shaper element is arranged over the optical refractive element for shaping the first incoherent light to generate first structured light with plural first optical patterns and shaping the second incoherent light to generate second structured light with plural second optical patterns, in which the first structured light and the second structured light are overlapped onto a region of space.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Inventor: Ming-Shu HSIAO
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Publication number: 20230135072Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.Type: ApplicationFiled: December 29, 2022Publication date: May 4, 2023Applicant: United Microelectronics Corp.Inventors: Hao Che Feng, Hung Jen Huang, Hsin Min Han, Shih-Wei Su, Ming Shu Chiu, Pi-Hung Chuang, Wei-Hao Huang, Shao-Wei Wang, Ping Wei Huang
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Patent number: 11581438Abstract: The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.Type: GrantFiled: August 12, 2020Date of Patent: February 14, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hao Che Feng, Hung Jen Huang, Hsin Min Han, Shih-Wei Su, Ming Shu Chiu, Pi-Hung Chuang, Wei-Hao Huang, Shao-Wei Wang, Ping Wei Huang
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Patent number: 11543696Abstract: A liquid crystal element includes a substrate, a diffractive optical element layer, and a liquid crystal material. The diffractive optical element layer has an uneven surface. The liquid crystal material is between the substrate and the uneven surface of the diffractive optical element layer. The liquid crystal material is disposed contiguously with the uneven surface of the diffractive optical element layer.Type: GrantFiled: July 18, 2019Date of Patent: January 3, 2023Assignee: HIMAX TECHNOLOGIES LIMITEDInventors: Hung-Shan Chen, Ming-Syuan Chen, Ming-Shu Hsiao, Cheng-Hung Chi, Kuan-Ming Chen, Chin-Jung Tsai, Yi-Nung Liu
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Publication number: 20220413154Abstract: A line pattern projector includes a light source array, a lens and a diffractive microlens array. The light source array includes a plurality of light sources that emit light beams, wherein the plurality of light sources are arranged along a first direction. The lens is configured to collimate the light beams. The diffractive microlens array (MLA) is configured to diffract the collimated light beams thereby to project an illumination pattern, wherein a lens pitch of the diffractive MLA with respect to the first direction is wider than a lens pitch of the diffractive MLA with respect to a second direction. The illumination pattern is formed by overlapping multiple dot patterns that are projected by the light sources; and the illumination pattern includes a plurality of line light patterns in the first direction.Type: ApplicationFiled: June 22, 2022Publication date: December 29, 2022Applicant: HIMAX TECHNOLOGIES LIMITEDInventor: Ming-Shu Hsiao
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Publication number: 20220412729Abstract: A dot pattern projector includes a light source array, a lens and a diffracting unit. The light source array includes a plurality of light sources that emit light beams. The lens is configured to collimate the light beams. The diffracting unit is configured to diffract the collimated light beams thereby to project an illumination pattern, wherein the illumination pattern is formed by overlapping multiple dot patterns that are projected by different light sources or interlacing multiple dot patterns that are projected by different light sources.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: HIMAX TECHNOLOGIES LIMITEDInventor: Ming-Shu Hsiao
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Publication number: 20220252893Abstract: A light projection apparatus is disclosed, which includes a laser source, an adjustable optical element and a diffractive optical element. The laser source is configured to emit light. The adjustable optical element is arranged over the light source for refracting the light. The adjustable optical element is position adjustable or effective focal length adjustable. The diffractive optical element is arranged over the adjustable optical element for diffracting the light onto a region of space.Type: ApplicationFiled: February 9, 2021Publication date: August 11, 2022Inventor: Ming-Shu HSIAO
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Publication number: 20220217068Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network and multiple host computers executing multiple machines. At a first host computer, the method identifies and stores (i) multiple time values associated with several packet processing operations performed on a particular packet sent by a first machine executing on the first host computer, and (ii) a time value associated with packet transmission through the SDDC network from the first host computer to a second host computer that is a destination of the particular packet. The method provides the stored time values to a set of one or more controllers to process to identify multiple latencies experienced by multiple packets processed in the SDDC.Type: ApplicationFiled: March 21, 2022Publication date: July 7, 2022Inventors: Haoran Chen, Ming Shu, Xi Cheng, Feng Pan, Xiaoyan Jin, Caixia Jiang, Qiong Wang, Qi Wu
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Patent number: 11356362Abstract: Example methods and systems for a network management entity to perform adaptive packet flow monitoring. One example method may comprise receiving a request to monitor a packet flow between a first virtualized computing instance supported by a first host and a second virtualized computing instance supported by a second host. The method may also comprise activating a first set of checkpoints by instructing the first host and/or the second host to monitor the packet flow using the first set of checkpoints. The method may further comprise: in response to detecting a predetermined event based on first performance metric information associated with the packet flow, activating a second set of checkpoints by instructing the first host and/or the second host to monitor the packet flow using the second set of checkpoints.Type: GrantFiled: March 7, 2019Date of Patent: June 7, 2022Assignee: VMWARE, INC.Inventors: Ming Shu, Wenyu Zhang, Qiong Wang, Donghai Han
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Patent number: 11283699Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network and multiple host computers executing multiple machines. At a first host computer, the method identifies and stores (i) multiple time values associated with several packet processing operations performed on a particular packet sent by a first machine executing on the first host computer, and (ii) a time value associated with packet transmission through the SDDC network from the first host computer to a second host computer that is a destination of the particular packet. The method provides the stored time values to a set of one or more controllers to process to identify multiple latencies experienced by multiple packets processed in the SDDC.Type: GrantFiled: March 2, 2020Date of Patent: March 22, 2022Assignee: VMWARE, INC.Inventors: Haoran Chen, Ming Shu, Xi Cheng, Feng Pan, Xiaoyan Jin, Caixia Jiang, Qiong Wang, Qi Wu
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Publication number: 20220052199Abstract: The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.Type: ApplicationFiled: August 12, 2020Publication date: February 17, 2022Applicant: United Microelectronics Corp.Inventors: Hao Che Feng, Hung Jen Huang, Hsin Min Han, Shih-Wei Su, Ming Shu Chiu, Pi-Hung Chuang, Wei-Hao Huang, Shao-Wei Wang, Ping Wei Huang
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Patent number: 11240163Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network, several host computers executing several machines, and a set of one or more controllers. At the set of controllers, the method o receives, from a set of host computers, (i) a first set of time values associated with multiple packet processing operations performed on packets sent by a set of machines executing on the set of host computers and (ii) a second set of time values associated with packet transmission between host computers through the SDDC network. The method processes the first and second sets of time values to identify a set of latencies experienced by multiple packets processed and transmitted in the SDDC.Type: GrantFiled: March 2, 2020Date of Patent: February 1, 2022Assignee: VMWARE, INC.Inventors: Haoran Chen, Ming Shu, Xi Cheng, Feng Pan, Xiaoyan Jin, Caixia Jiang, Qiong Wang, Qi Wu
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Patent number: 11095545Abstract: Some embodiments provide a method for managing control packet usage within a physical network that implements a plurality of logical networks. The method receives a tunnel monitoring configuration for a logical network. The configuration specifies control packet usage for logical datapaths between logical ports of the logical network. The method maps the logical datapaths to tunnels between host computers that host data compute nodes (DCNs) corresponding to the logical ports. Based on the mappings, the method configures control packet modules executing on the host computers to generate control packets for monitoring the tunnels based on the specified control packet usage.Type: GrantFiled: October 22, 2019Date of Patent: August 17, 2021Assignee: VMWARE, INC.Inventors: Haoran Chen, Xiaoyan Jin, Ming Shu
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Publication number: 20210226875Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network and multiple host computers executing multiple machines. At a first host computer, the method identifies and stores (i) multiple time values associated with several packet processing operations performed on a particular packet sent by a first machine executing on the first host computer, and (ii) a time value associated with packet transmission through the SDDC network from the first host computer to a second host computer that is a destination of the particular packet. The method provides the stored time values to a set of one or more controllers to process to identify multiple latencies experienced by multiple packets processed in the SDDC.Type: ApplicationFiled: March 2, 2020Publication date: July 22, 2021Inventors: Haoran Chen, Ming Shu, Xi Cheng, Feng Pan, Xiaoyan Jin, Caixia Jiang, Qiong Wang, Qi Wu
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Publication number: 20210226898Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network, several host computers executing several machines, and a set of one or more controllers. At the set of controllers, the method o receives, from a set of host computers, (i) a first set of time values associated with multiple packet processing operations performed on packets sent by a set of machines executing on the set of host computers and (ii) a second set of time values associated with packet transmission between host computers through the SDDC network. The method processes the first and second sets of time values to identify a set of latencies experienced by multiple packets processed and transmitted in the SDDC.Type: ApplicationFiled: March 2, 2020Publication date: July 22, 2021Inventors: Haoran Chen, Ming Shu, Xi Cheng, Feng Pan, Xiaoyan Jin, Caixia Jiang, Qiong Wang, Qi Wu