Abstract: A diode structure includes a rectangular first doping region, and a second doping region surrounds the first doping region wherein the first doping region and the second doping region are separated by a first isolation structure. A third doping region surrounds the second doping region wherein the second doping region and the third doping region are separated by a second isolation structure. The first isolation structure, the second doping region, the second isolation structure and the third doping region are arranged in a quadruple concentric rectangular ring surrounding the first doping region.

Abstract: A method of forming a HVMOS transistor device is provided. A substrate is provided. A first insulation structure and a trench are formed in the substrate. A base region having a second conductivity type is formed, wherein the base region completely encompasses the trench. Next, a gate dielectric layer and a gate structure are formed in the trench and covering a portion of the first insulation structure. Then, a drain region and a source region are formed in the substrate at two respective sides of the gate structure, and the drain region and the source region comprise a first conductivity type complementary to the second conductivity type. A channel is defined between the source region and the drain region along a first direction.

Abstract: A diode structure includes a rectangular first doping region, and a second doping region surrounds the first doping region wherein the first doping region and the second doping region are separated by a first isolation structure. A third doping region surrounds the second doping region wherein the second doping region and the third doping region are separated by a second isolation structure. The first isolation structure, the second doping region, the second isolation structure and the third doping region are arranged in a quadruple concentric rectangular ring surrounding the first doping region.

Abstract: A method of forming a HVMOS transistor device is provided. A substrate is provided. A first insulation structure and a trench are formed in the substrate. A base region having a second conductivity type is formed, wherein the base region completely encompasses the trench. Next, a gate dielectric layer and a gate structure are formed in the trench and covering a portion of the first insulation structure. Then, a drain region and a source region are formed in the substrate at two respective sides of the gate structure, and the drain region and the source region comprise a first conductivity type complementary to the second conductivity type. A channel is defined between the source region and the drain region along a first direction.

Abstract: A HVMOS transistor device is provided. The HVMOS has a substrate, a gate structure, a drain region and a source region, a base region and a gate dielectric layer. The substrate has a first insulating structure disposed therein. The gate structure is disposed on the substrate and comprises a first portion covering a portion of the first insulating structure. The drain region and the source region are disposed in the substrate at two respective sides of the gate, and comprise a first conductivity type. The base region encompasses the source region, wherein the base region comprises a second conductivity type complementary to the first conductivity type. The gate dielectric layer is between the gate and the drain region, the base region and the substrate. The gate structure further comprises a second portion penetrating into the base region. A method of forming the HVMOS is further provided.

Abstract: A resonator filter includes a substrate, a bottom electrode formed on the substrate, a multi-layered coupling structure formed on the bottom electrode, a top electrode formed on the multi-layered coupling structure, a first piezoelectric layer sandwiched in between the bottom electrode and the multi-layered coupling structure, and a second piezoelectric layer sandwiched in between the multi-layered coupling structure and the top electrode. The multi-layered coupling structure includes at least an insulating material.

Abstract: A HVMOS transistor device is provided. The HVMOS has a substrate, a gate structure, a drain region and a source region, a base region and a gate dielectric layer. The substrate has a first insulating structure disposed therein. The gate structure is disposed on the substrate and comprises a first portion covering a portion of the first insulating structure. The drain region and the source region are disposed in the substrate at two respective sides of the gate, and comprise a first conductivity type. The base region encompasses the source region, wherein the base region comprises a second conductivity type complementary to the first conductivity type. The gate dielectric layer is between the gate and the drain region, the base region and the substrate. The gate structure further comprises a second portion penetrating into the base region. A method of forming the HVMOS is further provided.

Abstract: A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract: A resonator filter includes a substrate, a bottom electrode formed on the substrate, a multi-layered coupling structure formed on the bottom electrode, a top electrode formed on the multi-layered coupling structure, a first piezoelectric layer sandwiched in between the bottom electrode and the multi-layered coupling structure, and a second piezoelectric layer sandwiched in between the multi-layered coupling structure and the top electrode. The multi-layered coupling structure includes at least an insulating material.

Abstract: A LDMOS structure including a semiconductor substrate, a drain region, a lightly doped drain (LDD) region, a source region and a gate structure is provided. The substrate has a trench. The drain region is formed in the semiconductor substrate under the trench. A LDD region is formed in the semiconductor substrate at a sidewall of the trench. The source region is formed in the semiconductor substrate. The gate structure is formed on a surface of the semiconductor substrate above the LDD region between the drain region and the source region. A method for manufacturing the LDMOS structure is also provided.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: A transistor device and a manufacturing method thereof are provided. The transistor device includes a substrate, a first well, a second well, a shallow trench isolation (STI), a source, a drain and a gate. The first well is disposed in the substrate. The second well is disposed in the substrate. The STI is disposed in the second well. The STI has at least one floating diffusion island. The source is disposed in the first well. The drain is disposed in the second well. The electric type of the floating diffusion island is different from or the same with that of the drain. The gate is disposed above the first well and the second well, and partially overlaps the first well and the second well.

Abstract: A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Abstract: A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Abstract: A transistor device and a manufacturing method thereof are provided. The transistor device includes a substrate, a first well, a second well, a shallow trench isolation (STI), a source, a drain and a gate. The first well is disposed in the substrate. The second well is disposed in the substrate. The STI is disposed in the second well. The STI has at least one floating diffusion island. The source is disposed in the first well. The drain is disposed in the second well. The electric type of the floating diffusion island is different from or the same with that of the drain. The gate is disposed above the first well and the second well, and partially overlaps the first well and the second well.