Abstract: Fabricating a dual-trench alternating phase shift mask (PSM) is disclosed. A chromium layer over a mask layer, which is over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer is dry etched according to deep trenches of a PSM design. The quartz layer is dry etched a first number of times through a first photoresist layer applied over the chromium layer and patterned according to the deep trenches of the PSM design by using backside ultraviolet exposure. The mask layer is dry etched again, according to shallow trenches of the PSM design. The quartz layer is dry etched a second number of times through a second photoresist layer applied over the chromium layer and patterned according to the shallow trenches of the PSM design by using backside ultraviolet exposure.

Abstract: Fabricating a dual-trench alternating phase shift mask (PSM) is disclosed. A chromium layer over a mask layer, which is over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer is dry etched according to deep trenches of a PSM design. The quartz layer is dry etched a first number of times through a first photoresist layer applied over the chromium layer and patterned according to the deep trenches of the PSM design by using backside ultraviolet exposure. The mask layer is dry etched again, according to shallow trenches of the PSM design. The quartz layer is dry etched a second number of times through a second photoresist layer applied over the chromium layer and patterned according to the shallow trenches of the PSM design by using backside ultraviolet exposure.

Abstract: Fabricating a dual-trench alternating phase shift mask (PSM) is disclosed. A chromium layer over a mask layer, which is over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer is dry etched according to deep trenches of a PSM design. The quartz layer is dry etched a first number of times through a first photoresist layer applied over the chromium layer and patterned according to the deep trenches of the PSM design by using backside ultraviolet exposure. The mask layer is dry etched again, according to shallow trenches of the PSM design. The quartz layer is dry etched a second number of times through a second photoresist layer applied over the chromium layer and patterned according to the shallow trenches of the PSM design by using backside ultraviolet exposure.

Abstract: The present disclosure provides a method for reducing or eliminating residual surface charge from a wafer during a semiconductor fabrication process. Because metal etching and photo resist ashing may result in a surface charge, performing a wet cleaning process directly after the ashing may increase corrosion to metal surfaces. This corrosion may be caused by an electro-chemical reaction that occurs between the surface charge and a solvent used in the wet cleaning process. To prevent this, the present disclosure introduces a water vapor treatment between the ashing and the wet cleaning processes. The water vapor treatment, which may be performed in-situ, provides an electrically neutral path that carries the surface charge from the surface of the wafer to electrical ground. By reducing or eliminating the surface charge, the water vapor treatment lessens or prevents corrosion to metal areas.

Abstract: A parallel ruler comprises a frame, and a plurality of gauges disposed in a flat portion of the frame. The gauges have compressible parts protruding downward beyond a lower surface of the frame for measuring a distance to a plane.

Abstract: A test keys structure comprises a plurality of test keys in scribe lines of a control monitor wafer. Between 50 and 400 test keys are formed on the control monitor wafer, and each of the plurality of test keys has an area of at least 1E6?m2.

Abstract: A method of early and effective detection of defects in a metal patterning process is described. A test keys structure is provided comprising a plurality of test keys in scribe lines of a control monitor wafer wherein more than 300 test keys are formed on a control monitor wafer and wherein each of the plurality of test keys has an area of at least 106 ?m2. A metal layer is deposited on the control monitor wafer. A dielectric layer is deposited overlying the metal layer. Thereafter, the control monitor wafer is tested using the plurality of test keys.

Abstract: Fabricating a dual-trench alternating phase shift mask (PSM) is disclosed. A chromium layer over a mask layer, which is over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer is dry etched according to deep trenches of a PSM design. The quartz layer is dry etched a first number of times through a first photoresist layer applied over the chromium layer and patterned according to the deep trenches of the PSM design by using backside ultraviolet exposure. The mask layer is dry etched again, according to shallow trenches of the PSM design. The quartz layer is dry etched a second number of times through a second photoresist layer applied over the chromium layer and patterned according to the shallow trenches of the PSM design by using backside ultraviolet exposure.

Abstract: A method and system for implementing a variable function circuit within a single semiconductor chip. The semiconductor chip can be configured as a single circuit that provides varying functions according to extrinsic conditions. The single circuit can be permitted to be switched between a particular function and a different particular function, thereby promoting a decreased complexity in circuit design and a decrease in physical dimensions necessary to manufacture the semiconductor chip. Additionally, at least one portion of the semiconductor chip may be designated to the particular function and at least one other portion of the semiconductor chip to the different particular function. The semiconductor chip may thus act as a function switch.

Abstract: A semiconductor calibration wafer that has no charge effect is disclosed. The calibration wafer has a substrate layer and a conductive metal layer. The conductive metal layer completely covers the substrate layer, and has a critical dimension (CD) bar corresponding to a desired CD. The substrate layer may be an oxide layer or another type of substrate layer, whereas the conductive metal layer may be an aluminum layer, a copper layer, or another type of conductive metal layer. Where the calibration wafer is used in conjunction with a scanning electron microscope (SEM) to monitor the CD, the electrons ejected by the SEM do not remain on the semiconductor calibration wafer, but instead are carried away via the conductive metal layer. The calibration wafer is thus not vulnerable to the charge effect.

Abstract: A new method for detecting blind holes in the contact layer of a multi-chip semiconductor test wafer makes use of the fact that if the hole is not a blind hole, a subsequent etch step extends the hole a predetermined distance into the layer immediately underlying the contact layer. After a predetermined number of holes have been etched through the contact layer and for a predetermined distance into the layer underlying the contact layer, the contact layer is stripped to expose the holes in the underlying layer. These holes are scanned optically by a commercial apparatus that ordinarily detects wafer defects that resemble the holes. The missing holes are detected by comparing the holes of different chips on the test wafer. The test is particularly useful with a high density plasma etch because these holes typically have a very small diameter in relation to the thickness of the contact layer.

Abstract: A method of early and effective detection of defects in a metal patterning process is described. A test keys structure is provided comprising a plurality of test keys in scribe lines of a control monitor wafer wherein more than 300 test keys are formed on a control monitor wafer and wherein each of the plurality of test keys has an area of at least 106 &mgr;m2. A metal layer is deposited on the control monitor wafer. A dielectric layer is deposited overlying the metal layer. Thereafter, the control monitor wafer is tested using the plurality of test keys.

Abstract: A semiconductor calibration wafer that has no charge effect is disclosed. The calibration wafer has a substrate layer and a conductive metal layer. The conductive metal layer completely covers the substrate layer, and has a critical dimension (CD) bar corresponding to a desired CD. The substrate layer may be an oxide layer or another type of substrate layer, whereas the conductive metal layer may be an aluminum layer, a copper layer, or another type of conductive metal layer. Where the calibration wafer is used in conjunction with a scanning electron microscope (SEM) to monitor the CD, the electrons ejected by the SEM do not remain on the semiconductor calibration wafer, but instead are carried away via the conductive metal layer. The calibration wafer is thus not vulnerable to the charge effect.

Abstract: A method and system for implementing a variable function circuit within a single semiconductor chip. The semiconductor chip can be configured as a single circuit that provides varying functions according to extrinsic conditions. The single circuit can be permitted to be switched between a particular function and a different particular function, thereby promoting a decreased complexity in circuit design and a decrease in physical dimensions necessary to manufacture the semiconductor chip. Additionally, at least one portion of the semiconductor chip may be designated to the particular function and at least one other portion of the semiconductor chip to the different particular function. The semiconductor chip may thus act as a function switch.

Abstract: An improved seasoning process for a plasma etching chamber is described. This has been achieved by increasing the RF power to both the wafer and the walls of the chamber during seasoning. Additionally, the gas that is used is at a pressure of about 10 mTorr and has the following composition: chlorine about 90% and oxygen about 10%. By observing the optical emission spectrum during seasoning (notably lines due to the SiClx species) it is confirmed that, under these conditions, seasoning is completed by using only a single wafer for about 100 seconds.

Abstract: A process is described for etching contact holes though a dielectric layer down to a silicon surface. Initial etching, until the silicon is exposed, is performed in a suitable plasma environment under high RF power. This results in damage to the newly exposed silicon surface. Said damage is repaired by exposing the silicon and the photoresist to an atmosphere that includes carbon tetrafluoride and atomic oxygen. The latter oxidizes the damaged layer, allowing it to be removed by the former. Much of the photoresist is also removed by the atomic oxygen, any that still remains being then removed using a wet etch. At the user's option, the silicon may be allowed to overetch during the high RF power application and/or a low power RF step may be introduced to partially remove silicon surface damage prior to the atomic oxygen treatment.

Abstract: A method for etching access opening to aluminum alloy wire bonding pads of integrated circuit chips is described wherein a polymer layer is in-situ deposited into the opening after the bonding pad has been exposed by dry etching of a passivation layer. The passivation layer, is first etched with fluorocarbon etchants and then a TiN ARC layer is removed from over the aluminum bonding pad with etchants which may contain chlorine either as etch components or as a contaminant in an etchant such as SF.sub.6 non-volatile chlorine containing residues including AlCl.sub.3 and trapped Cl.sub.2, are left behind after the ARC layer has been removed. These cause corrosion of the bonding pad when exposed to atmospheric moisture. The polymer layer deposited immediately after the pad surface is exposed by the etchant, provides a temporary seal over the aluminum bonding pad, protecting it from exposure to moisture during subsequent processing steps.