Patents by Inventor Ming Siu

Ming Siu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060149803
    Abstract: A multipurpose functional unit is configurable to support a number of operations including multiply-add and format conversion operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and logical test operations.
    Type: Application
    Filed: November 10, 2004
    Publication date: July 6, 2006
    Applicant: NVIDIA CORPORATION
    Inventors: Ming Siu, Stuart Oberman
  • Publication number: 20060101242
    Abstract: A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations.
    Type: Application
    Filed: November 10, 2004
    Publication date: May 11, 2006
    Applicant: NVIDIA CORPORATION
    Inventors: Ming Siu, Stuart Oberman
  • Publication number: 20060101243
    Abstract: A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations.
    Type: Application
    Filed: November 10, 2004
    Publication date: May 11, 2006
    Applicant: NVIDIA CORPORATION
    Inventors: Ming Siu, Stuart Oberman
  • Publication number: 20060101244
    Abstract: A multipurpose functional unit is configurable to support a number of operations including floating-point and integer multiply-add, operations as well as other integer and/or floating-point arithmetic operations, Boolean operations, comparison testing operations, and format conversion operations.
    Type: Application
    Filed: November 10, 2004
    Publication date: May 11, 2006
    Applicant: NVIDIA CORPORATION
    Inventors: Ming Siu, Stuart Oberman
  • Publication number: 20060012603
    Abstract: An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multiple banks. A collector unit coupled to each bank gathers source operands needed to process a program instruction as the source operands output from one or more banks. The collector unit outputs the source operands to an execution unit when all of the source operands needed to process the program instruction have been gathered.
    Type: Application
    Filed: July 13, 2004
    Publication date: January 19, 2006
    Inventors: John Lindholm, Ming Siu, Simon Moy, Samuel Liu, John Nickolls
  • Patent number: 6397238
    Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: May 28, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stuart Oberman, Norbert Juffa, Ming Siu, Frederick D Weber, Ravikrishna Cherukuri
  • Patent number: 6393554
    Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: May 21, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stuart F. Oberman, Ming Siu, Ravi Krishna Cherukuri
  • Patent number: 6381625
    Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: April 30, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stuart Oberman, Norbert Juffa, Ming Siu, Frederick D Weber, Ravikrishna Cherukuri
  • Publication number: 20010023425
    Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.
    Type: Application
    Filed: February 12, 2001
    Publication date: September 20, 2001
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Stuart Oberman, Norbert Juffa, Ming Siu, Frederick D. Weber, Ravikrishna Cherukuri
  • Publication number: 20010010051
    Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.
    Type: Application
    Filed: February 12, 2001
    Publication date: July 26, 2001
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Stuart Oberman, Norbert Juffa, Ming Siu, Frederick D. Weber, Ravikrishna Cherukuri
  • Patent number: 6223198
    Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: April 24, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stuart Oberman, Norbert Juffa, Ming Siu, Frederick D Weber, Ravikrishna Cherukuri
  • Patent number: 6085213
    Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: July 4, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stuart Oberman, Ming Siu
  • Patent number: 6038583
    Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: March 14, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stuart Oberman, Ming Siu
  • Patent number: 6026483
    Abstract: A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and comprises a partial product generator, a selection logic unit, and an adder. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. The multiplier is also configured to receive a first control signal indicative of whether signed or unsigned multiplication is to be performed and a second control signal indicative of whether vector multiplication is to be performed. The multiplier is configured to calculate an effective sign for the multiplier and multiplicand operands based upon each operand's most significant bit and the control signal. The effective signs may then be used by the partial product generation unit and the selection logic to create and select a number of partial products according to Booth's algorithm.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: February 15, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stuart F. Oberman, Ravikrishna Cherukuri, Ming Siu