Abstract: A method of operating an electronic device is disclosed. The method includes generating an initial time value, generating an initial time stamp based on the initial time value, and transmitting the initial time stamp. The initial time stamp has a number of bits. For a set period of time, the time stamp is updated and the updated time stamp is transmitted from the electronic device. After the set period of time, the time stamp is adjusted by a residual time amount and the adjusted time stamp is transmitted from the electronic device. Other implementations are disclosed.

Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.

Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.

Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.

Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.

Abstract: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

Abstract: Techniques for power management in a multi-processor system are disclosed. One of the processors in the system monitors whether all threads on all central processing unit (CPU) cores in the multi-processor system halt, and send a message to a south bridge to cause at least a part of the system to enter a low power state if all threads in the multi-processor system halt. The processor sends another message to the south bridge to cause at least a part of the multi-processor system to wake up if at least one thread on any CPU core in the multi-processor system exits a halt.

Abstract: An ultra-low power crystal oscillator architecture that draws less than 2 ?A during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 ?A.

Abstract: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

Abstract: An ultra-low power crystal oscillator architecture that draws less than 2 ?A during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 ?A.