Patents by Inventor Ming-Sung KUO

Ming-Sung KUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240347396
    Abstract: A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wx1 measured along a first axis. The bottom wafer pattern includes a first part with a width Wx2 measured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas: Tx > Dx - Sx ; ? Tx < Dx - Sx + Wx ? 2 ; ? Tx > Sx ; ? Tx < Dx - Sx + Wx ? 1 ; wherein, Tx represents a searching distance for finding an end-point of the first portion or an end-point of the first part; and Sx represents an actual shifting amount of the first portion.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 17, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Sung Kuo, Hsun-Kuo Hsiao, Chung-Cheng Chen, Po-Wei Chen
  • Publication number: 20240321765
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Publication number: 20240312692
    Abstract: Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hao-Yi Tsai, Hung-Yi Kuo, Ming Hung Tseng
  • Patent number: 12057353
    Abstract: A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wx1 measured along a first axis. The bottom wafer pattern includes a first part with a width Wx2 measured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas: Tx>Dx?Sx; Tx<Dx?Sx+Wx2; Tx>Sx; Tx<Dx?Sx+Wx1; wherein, Tx represents a searching distance for finding an end-point of the first portion or an end-point of the first part; and Sx represents an actual shifting amount of the first portion.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Sung Kuo, Hsun-Kuo Hsiao, Chung-Cheng Chen, Po-Wei Chen
  • Patent number: 12040283
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Publication number: 20230045223
    Abstract: A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wx1 measured along a first axis. The bottom wafer pattern includes a first part with a width Wx2 measured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas: Tx>Dx?Sx; Tx<Dx?Sx+Wx2; Tx>Sx; Tx<Dx?Sx+Wx1; wherein, Tx represents a searching distance for finding an end-point of the first portion or an end-point of the first part; and Sx represents an actual shifting amount of the first portion.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Sung Kuo, Hsun-Kuo Hsiao, Chung-Cheng Chen, Po-Wei Chen
  • Patent number: 11195737
    Abstract: An apparatus for storing and transporting semiconductor elements includes a first portion and a second portion. The first portion includes a first front side wall, a first rear side wall, a top wall, and at least one pin holder integrally extending from the first rear side wall. The second portion includes a second front side wall, a second rear side wall, a bottom wall, and at least one pivotal pin structure integrally coupled with and extending from the second rear side wall. The at least one pivotal pin structure comprises a shaft, and a head connected with the shaft. The at least one pin holder defines a cavity sized and shaped to accept the head of the at least one pivotal pin structure. The first portion and the second portion are pivotally movable between an open configuration and a closed container configuration.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Sung Kuo, Jhih-Yuan Yang, Po-Wei Chen, Fang-yu Liu, Ping-Cheng Ko, Chung-Cheng Chen
  • Patent number: 9423359
    Abstract: An electromagnetic inspection tool which includes a stage configured to support a wafer having a first surface and an emitter configured to emit electromagnetic waves to be incident on the first surface. The electromagnetic inspection tool further includes a detector configured to detect electromagnetic waves returned from the first surface and a charging mechanism configured to charge the first surface. A method of electromagnetically inspecting a wafer which includes loading a wafer having a first surface onto a stage and emitting electromagnetic waves to be incident on the first surface. The method further includes detecting electromagnetic waves returned from the first surface and charging the first surface prior to detecting the electromagnetic waves returned from the first surface.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: August 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Sung Kuo, Chiun-Chieh Su, Chih-Shun Chu, To-Yu Chen
  • Publication number: 20150002835
    Abstract: An electromagnetic inspection tool which includes a stage configured to support a wafer having a first surface and an emitter configured to emit electromagnetic waves to be incident on the first surface. The electromagnetic inspection tool further includes a detector configured to detect electromagnetic waves returned from the first surface and a charging mechanism configured to charge the first surface. A method of electromagnetically inspecting a wafer which includes loading a wafer having a first surface onto a stage and emitting electromagnetic waves to be incident on the first surface. The method further includes detecting electromagnetic waves returned from the first surface and charging the first surface prior to detecting the electromagnetic waves returned from the first surface.
    Type: Application
    Filed: June 26, 2013
    Publication date: January 1, 2015
    Inventors: Ming-Sung KUO, Chiun-Chieh SU, Chih-Shun CHU, To-Yu CHEN