Abstract: A method of forming an EEPROM memory cell on a semiconductor substrate, comprises forming a first dielectric layer on the substrate, a gate electrode of a select transistor and a first layer of a floating gate electrode of an EEPROM device on the dielectric layer, ion implanted source/drain regions in the substrate adjacent to the gate electrode and the first layer of the floating gate electrode proximate to at least the periphery of the gate electrode and the first layer of the floating gate electrode. The central region of the ion implanted regions is between the gate electrode and the first layer of the floating gate electrode.

Abstract: A read-only-memory having a plurality of very narrow, closely spaced gate electrodes spanning the distance between source and drain regions. The gate electrodes consist of first and second alternating polycrystalline silicon lines having vertical sidewalls. The first lines have tapered sidewall spacers. The second lines are entirely contained between the first lines without overlap of the first lines.

Abstract: A threshold circuit that uses capacitors to form a weighted sum of its inputs uses a two stage capacitor structure. The two stages form a compact structure that increases the number of input signals that can be handled and increases the flexibility in assigning the weights to the input signals. Capacitor electrodes for the input signals are arranged in two sets and the electrodes of each set are electrostatically coupled to first and second electrodes. Third and fourth electrodes, which extend from the first and second electrodes respectively, are electrostatically coupled to a unitary structure of fifth and sixth electrodes where their voltages are summed. The fifth and sixth electrodes are conductively connected to the gate of an FET threshold circuit that responds to the weighted and summed input signals.

Abstract: A method for making a Read Only Memory having spaced source and drain regions in a substrate and a plurality of closely spaced gate electrodes on the surface, spanning the distance between the source and drain. The method features the fabrication of a double density polysilicon word line structure for a given integrated circuit chip area. The method also features the formation of a first and a second code ion implant which uses self-alignment techniques, rather than using lithography techniques.