Patents by Inventor Ming-Tak Leung
Ming-Tak Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240129146Abstract: A first communication device generates an Operation, Administration, and Maintenance (OAM) frame that includes i) OAM message content and ii) an OAM frame header outside of the OAM message content, wherein generating the OAM frame comprises generating the OAM frame header to include information that signals one of i) a low power sleep (LPS) request, and ii) a wake-up request (WUR). The first communication device transmits the OAM frame to a second communication device via a communication medium to signal to the second communication device the one of i) the LPS request, and ii) the WUR.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Inventors: Ming-Tak LEUNG, Bizhan ABEDINZADEH, Hon Wai FUNG, Liang ZHU, Der-Ren CHU
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Patent number: 11855791Abstract: A first communication device generates an Operation, Administration, and Maintenance (OAM) frame that includes i) OAM message content and ii) an OAM frame header outside of the OAM message content, wherein generating the OAM frame comprises generating the OAM frame header to include information that signals one of i) a low power sleep (LPS) request, and ii) a wake-up request (WUR). The first communication device transmits the OAM frame to a second communication device via a communication medium to signal to the second communication device the one of i) the LPS request, and ii) the WUR.Type: GrantFiled: October 6, 2021Date of Patent: December 26, 2023Assignee: Marvell Asia Pte LtdInventors: Ming-Tak Leung, Bizhan Abedinzadeh, Hon Wai Fung, Liang Zhu, Der-Ren Chu
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Publication number: 20220303109Abstract: A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.Type: ApplicationFiled: March 21, 2022Publication date: September 22, 2022Inventors: Jeff Junwei Zheng, Ming-Tak Leung, Atif Ahmad, Lenin Patra
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Publication number: 20220109583Abstract: A first communication device generates an Operation, Administration, and Maintenance (OAM) frame that includes i) OAM message content and ii) an OAM frame header outside of the OAM message content, wherein generating the OAM frame comprises generating the OAM frame header to include information that signals one of i) a low power sleep (LPS) request, and ii) a wake-up request (WUR). The first communication device transmits the OAM frame to a second communication device via a communication medium to signal to the second communication device the one of i) the LPS request, and ii) the WUR.Type: ApplicationFiled: October 6, 2021Publication date: April 7, 2022Inventors: Ming-Tak LEUNG, Bizhan ABEDINZADEH, Hon Wai FUNG, Liang ZHU, Der-Ren CHU
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Patent number: 10644834Abstract: A method for communication, including, in a Physical Layer (PHY) transceiver, selecting a transmission bitrate from a plurality of transmission bitrates, for transmitting over a media interface bits received from an external device. The received bits are processed by generating, using a framing and encoding scheme that depends on at least the selected transmission bitrate, frames having a common frame length among the framing and encoding schemes. The frames are encoded to produce code words of a predefined Forward Error Correction Code (FEC) code, using a single FEC encoder that accepts a number of bits for encoding equal to the frame length. Sub-units of the code words are mapped into symbols using one of at least two mapping schemes that employ different voltage amplitude levels to define a transmission symbol, the mapping scheme being selected according to the selected transmission bitrate. The symbols are transmitted over the media interface.Type: GrantFiled: July 31, 2018Date of Patent: May 5, 2020Assignee: MARVELL INTERNATIONAL LTD.Inventors: Brett Anthony McClellan, Ming-Tak Leung, Xing Wu
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Patent number: 7027501Abstract: According to the present invention, methods and apparatus are provided for improving the signal quality of received transmission. An adaptive equalizer includes multiple output delay lines. One output delay line is configured to provide gradient elements. Another output delay line is configured with coefficient multipliers calculated using the gradient elements. The coefficient multipliers are used to alter a received signal to more closely correspond to an expected signal. The adaptive equalizer can be used in systems such as optical transceivers.Type: GrantFiled: February 27, 2002Date of Patent: April 11, 2006Assignee: Tripath Technology Inc.Inventors: Adya S. Tripathi, Delon Hanson, Kar Shing Chiu, Ming-Tak Leung, Raman Dakshinamurthy, Ki Chun Fu
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Patent number: 6728928Abstract: A Viterbi detector includes circuitry for receiving an NRZ encoded received signal in an EEPR4 channel to decode the signal according to &lgr;k(i)=(zk−yk(i))2−&agr;(i), wherein &agr;(i) is m &agr;, &agr; is a positive constant, m is a number of transitions within the most current four symbol periods, &lgr;k(i) is a branch metric at time k for an ith Viterbi branch, k is a time period, zk is a received value at time k, &lgr;k(i) is a metric used to determine a next state of the Viterbi based upon a maximum likelihood evaluation for an ith branch, ak, ak−1, ak−2, ak−3 are received state values at respective time periods k, k−1, k−2, and k−3, and yk is an ideal sample associated with an ith branch. The detector is operated to decode a received data value by determining whether the received value is in a space containing first (90) and second (92) possible decode values.Type: GrantFiled: March 2, 2001Date of Patent: April 27, 2004Assignee: Texas Instruments IncorporatedInventors: Taehyun Jeon, Ming-Tak Leung, Leo Ki-Chun Fu, Younggyun Kim
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Patent number: 6704903Abstract: A branch metric computation using limited bits by clipping the dynamic range and/or approximating the square of the difference between a sample value and the target value by a lookup table or piecewise linear with comparable slopes.Type: GrantFiled: February 18, 2000Date of Patent: March 9, 2004Assignee: Texas Instruments IncorporatedInventors: Michael Ming Tak Leung, Leo Ki Chun Fu, Borivoje Nikolic, James Kar Shing Chiu
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Publication number: 20020184597Abstract: A Viterbi detector includes circuitry for receiving an NRZ encoded received signal in an EEPR4 channel to decode the signal according to &lgr;k(i)=(zk−yk(i))2−&agr;(i), wherein &agr;(i) is m &agr;, &agr; is a positive constant, m is a number of transitions within the most current four symbol periods, &lgr;k(i) is a branch metric at time k for an ith Viterbi branch, k is a time period, zk is a received value at time k, &lgr;k(i) is a metric used to determine a next state of the Viterbi based upon a maximum likelihood evaluation for an ith branch, ak, ak−1, ak−2, ak−3 are received state values at respective time periods k, k−1, k−2, and k−3, and yk is an ideal sample associated with an ith branch. The detector is operated to decode a received data value by determining whether the received value is in a space containing first (90) and second (92) possible decode values.Type: ApplicationFiled: March 2, 2001Publication date: December 5, 2002Inventors: Taehyun Jeon, Ming-Tak Leung, Leo Ki-Chun Fu, Younggyun Kim
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Patent number: 6081210Abstract: A method and system for encoding user data bits for magnetic recording channels that produces a stationary trellis and that limits the burst error propagation to three user bytes. The input data bits are grouped into even bytes and odd bytes. The even bytes are encoded first into even codewords, then each of the odd bytes is encoded into odd codewords based on the even codeword for the even byte preceding each odd byte and on the even codeword for the even byte following each odd byte. The encoding eliminates the most common error events associated with Partial Response Maximum Likelihood channels by: (i) disallowing sequences of four consecutive ones in the codewords, (ii) allowing sequences of three consecutive ones to begin only on certain bit positions in certain codewords, (iii) allowing only certain beginning sequences and ending sequences for odd and even codewords in specific situations, and (iv) changing specific bits in the odd and even codewords based on disallowed codeword sequences.Type: GrantFiled: May 13, 1998Date of Patent: June 27, 2000Assignee: Texas Instruments IncorporatedInventors: Borivoje Nikolic, Ming-Tak Leung
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Patent number: 6009534Abstract: The present invention includes a fractional interpretation circuit to be used to correct pre-write compensation for writing data on a disk. The present invention need not be limited to a three phase interpreter but could easily be extended to a 4X or 5X. This could simply be implemented by adding additional current paths from the capacitors to ground in order to incrementally change the slew rate and consequently the phase interpretation.Type: GrantFiled: June 1, 1998Date of Patent: December 28, 1999Assignee: Texas Instruments IncorporatedInventors: Kar-Shing Chiu, Ming-Tak Leung