Patents by Inventor Ming-Te Chen
Ming-Te Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250086437Abstract: An operating method of a fully homomorphic encrypted neural network model is provided, wherein the fully homomorphic encrypted neural network model includes a plurality of layers, and the method performed by a processor includes: for one of the plurality of layers, encrypting a plaintext input with a first encryption algorithm to generate a ciphertext vector, performing a convolution operation according to the ciphertext vector to generate a result vector, transforming the result vector into a plurality of result ciphertexts adopting a second encryption algorithm, inputting the plurality of result ciphertexts into an activation function to generate a plurality of encrypted activation values, and repacking the plurality of encrypted activation values to generate an output vector adopting the first encryption algorithm.Type: ApplicationFiled: December 19, 2023Publication date: March 13, 2025Applicants: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATIONInventors: Tzu-Li LIU, Yu-Te KU, Ming-Chien HO, Chih-Fan HSU, Wei-Chao CHEN, Feng-Hao LIU, Ming-Ching CHANG, Shih-Hao HUNG
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Publication number: 20250080320Abstract: An inference method for encrypted deep neural network model is executed by a computing device and includes: encoding a message according to a quantization parameter to generate a plaintext, encrypting the plaintext according to a private key to generate a ciphertext, sending the ciphertext to a deep neural network model to generate a ciphertext result, decrypting the ciphertext result according to the private key to generate a plaintext result, and decoding the plaintext result according to the quantization parameter to generate an inference result.Type: ApplicationFiled: January 10, 2024Publication date: March 6, 2025Applicants: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATIONInventors: Yu-Te KU, Chih-Fan HSU, Wei-Chao CHEN, Feng-Hao LIU, Ming-Ching CHANG, Shih-Hao HUNG
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Publication number: 20250072028Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.Type: ApplicationFiled: November 13, 2024Publication date: February 27, 2025Inventors: MING-TE CHEN, HUI-TING TSAI, JUN HE, KUO-FENG YU, CHUN HSIUNG TSAI
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Publication number: 20250038998Abstract: The present invention relates to a cyber security authentication method. The method includes the following steps: in a user device: randomly generating an ephemeral decryption key, transmitting the ephemeral decryption key to a security server, and retrieving a key index from the security server; encrypting an identity information based on a part of the ephemeral decryption key to generate an electronic digital signature and an authentication token; and combining the key index, the electronic digital signature, and the authentication token to form an ephemeral certificate and transmitting the ephemeral certificate to a non-Internet electronic device; and in the non-Internet electronic device: parsing the ephemeral certificate to obtain the key index; and forwarding the key index to the security server via a transport connection including the user device to retrieve the ephemeral decryption key from the security server based on the key index.Type: ApplicationFiled: May 30, 2024Publication date: January 30, 2025Inventors: Jia-You JIANG, Tsu-Pin WENG, Yuan-Sheng CHEN, Jung-Hua LO, Yin-Te Tsai, Wen-Hsing KUO, Ming-Feng LU
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Publication number: 20250031458Abstract: A semiconductor structure is provided in the present invention, including a substrate, a deep N-well formed in the substrate, a first well formed in the deep N-well, a first gate formed on the first well, a first source and a first drain formed respectively at two sides of the first gate in the first well, a first doped region formed in the first well, and a metal interconnect electrically connected with the first source and the first doped region, wherein an area of the deep N-well multiplied by a first parameter is a first factor, an area of the first gate multiplied by a second parameter is a second factor, and an area of the metal interconnect divided by a sum of the first factor and the second factor is less than a specification value.Type: ApplicationFiled: September 5, 2023Publication date: January 23, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Te Lin, Wen-Chun Chang, Sung-Nien Kuo, Tzu-Chun Chen, Kuan-Cheng Su
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Patent number: 12170327Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.Type: GrantFiled: August 10, 2021Date of Patent: December 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Te Chen, Hui-Ting Tsai, Jun He, Kuo-Feng Yu, Chun Hsiung Tsai
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Publication number: 20240387734Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chandrashekhar Prakash SAVANT, Kin Shun CHONG, Tien-Wei YU, Chia-Ming TSAI, Ming-Te CHEN
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Publication number: 20240379825Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: MING-TE CHEN, HUI-TING TSAI, JUN HE, KUO-FENG YU, CHUN HSIUNG TSAI
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Patent number: 12142682Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.Type: GrantFiled: July 30, 2021Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chandrashekhar Prakash Savant, Kin Shun Chong, Tien-Wei Yu, Chia-Ming Tsai, Ming-Te Chen
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Publication number: 20240234530Abstract: A device includes: a stack of nanostructure channels over a substrate; a gate structure wrapping around the stack; and a source/drain region on the substrate. The source/drain region includes: a first epitaxial layer in direct contact with the channels; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having higher germanium concentration than the first epitaxial layer. The device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer that is in direct contact with the source/drain region.Type: ApplicationFiled: June 6, 2023Publication date: July 11, 2024Inventors: Chun-Hsiung TSAI, Yu-Ming LIN, Kuo-Feng YU, Yu-Ting LIN, Ming-Te CHEN, Yi-Hsiu HUANG
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Patent number: 11978675Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.Type: GrantFiled: November 22, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
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Publication number: 20230377994Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.Type: ApplicationFiled: August 3, 2023Publication date: November 23, 2023Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
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Publication number: 20230268231Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
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Patent number: 11670553Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.Type: GrantFiled: August 9, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
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Publication number: 20220320319Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.Type: ApplicationFiled: August 10, 2021Publication date: October 6, 2022Inventors: MING-TE CHEN, HUI-TING TSAI, JUN HE, KUO-FENG YU, CHUN HSIUNG TSAI
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Patent number: 11329160Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.Type: GrantFiled: February 16, 2017Date of Patent: May 10, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ta Wu, Shiu-Ko Jangjian, Chung-Ren Sun, Ming-Te Chen, Ting-Chun Wang, Jun-Jie Cheng
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Publication number: 20220084890Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.Type: ApplicationFiled: November 22, 2021Publication date: March 17, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Ming-Te CHEN, Tien-Wei YU
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Publication number: 20220059684Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.Type: ApplicationFiled: July 30, 2021Publication date: February 24, 2022Inventors: Chandrashekhar Prakash SAVANT, Kin Shun CHONG, Tien-Wei YU, Chia-Ming TSAI, Ming-Te CHEN
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Patent number: 11232953Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.Type: GrantFiled: September 17, 2019Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Miao-Syuan Fan, Ching-Hua Lee, Ming-Te Chen, Jung-Wei Lee, Pei-Wei Lee
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Publication number: 20210366778Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu