Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Abstract: A device includes: a stack of nanostructure channels over a substrate; a gate structure wrapping around the stack; and a source/drain region on the substrate. The source/drain region includes: a first epitaxial layer in direct contact with the channels; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having higher germanium concentration than the first epitaxial layer. The device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer that is in direct contact with the source/drain region.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.