Patents by Inventor Ming-Te Chen

Ming-Te Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250072028
    Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Inventors: MING-TE CHEN, HUI-TING TSAI, JUN HE, KUO-FENG YU, CHUN HSIUNG TSAI
  • Patent number: 12170327
    Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Te Chen, Hui-Ting Tsai, Jun He, Kuo-Feng Yu, Chun Hsiung Tsai
  • Publication number: 20240387734
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chandrashekhar Prakash SAVANT, Kin Shun CHONG, Tien-Wei YU, Chia-Ming TSAI, Ming-Te CHEN
  • Publication number: 20240379825
    Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: MING-TE CHEN, HUI-TING TSAI, JUN HE, KUO-FENG YU, CHUN HSIUNG TSAI
  • Patent number: 12142682
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chandrashekhar Prakash Savant, Kin Shun Chong, Tien-Wei Yu, Chia-Ming Tsai, Ming-Te Chen
  • Publication number: 20240234530
    Abstract: A device includes: a stack of nanostructure channels over a substrate; a gate structure wrapping around the stack; and a source/drain region on the substrate. The source/drain region includes: a first epitaxial layer in direct contact with the channels; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having higher germanium concentration than the first epitaxial layer. The device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer that is in direct contact with the source/drain region.
    Type: Application
    Filed: June 6, 2023
    Publication date: July 11, 2024
    Inventors: Chun-Hsiung TSAI, Yu-Ming LIN, Kuo-Feng YU, Yu-Ting LIN, Ming-Te CHEN, Yi-Hsiu HUANG
  • Patent number: 11978675
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
  • Publication number: 20230377994
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
  • Publication number: 20230268231
    Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
  • Patent number: 11670553
    Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
  • Publication number: 20220320319
    Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.
    Type: Application
    Filed: August 10, 2021
    Publication date: October 6, 2022
    Inventors: MING-TE CHEN, HUI-TING TSAI, JUN HE, KUO-FENG YU, CHUN HSIUNG TSAI
  • Patent number: 11329160
    Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta Wu, Shiu-Ko Jangjian, Chung-Ren Sun, Ming-Te Chen, Ting-Chun Wang, Jun-Jie Cheng
  • Publication number: 20220084890
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Ming-Te CHEN, Tien-Wei YU
  • Publication number: 20220059684
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 24, 2022
    Inventors: Chandrashekhar Prakash SAVANT, Kin Shun CHONG, Tien-Wei YU, Chia-Ming TSAI, Ming-Te CHEN
  • Patent number: 11232953
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: January 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Miao-Syuan Fan, Ching-Hua Lee, Ming-Te Chen, Jung-Wei Lee, Pei-Wei Lee
  • Publication number: 20210366778
    Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
  • Patent number: 11183431
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
  • Patent number: 11088029
    Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
  • Patent number: 11081584
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar Prakash Savant, Kin Shun Chong, Tien-Wei Yu, Chia-Ming Tsai, Ming-Te Chen
  • Publication number: 20210082707
    Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Miao-Syuan FAN, Ching-Hua LEE, Ming-Te CHEN, Jung-Wei LEE, Pei-Wei LEE